Drive circuit and drive method thereof, and panel and drive method thereof

A panel, comprising:

• a substrate, an array layer and an electrode array layer, wherein:
• the array layer is on a side of the substrate;
• the electrode array layer is on a side of the array layer away from the substrate;
• and the array layer includes an active layer, a gate metal layer and a source/drain metal layer;
• the substrate includes a plurality of drive units arranged in an array, a plurality of scan line groups and a plurality of data line groups;
• the scan line group includes first scan lines and second scan lines adjacent to the first scan lines, extending in a first direction;
• and the data line group includes first data lines and second data lines adjacent to the first data lines, extending in a second direction, wherein the first direction is perpendicular with the second direction;
• the electrode array layer includes a plurality of drive electrodes arranged in an array;
• the drive electrodes correspond to the drive units;
• and the drive unit includes a first transistor, a second transistor and a first capacitor;
• a gate of the first transistor is electrically connected to the first scan line;
• a source of the first transistor is electrically connected to the first data line;
• a drain of the first transistor is electrically connected to the drive electrode;
• and the drive electrode is electrically connected to a first electrode of the first capacitor;
• a gate of the second transistor is electrically connected to the second scan line;
• a source of the second transistor is electrically connected to the second data line;
• and a drain of the second transistor is electrically connected to a second electrode of the first capacitor;
• the scan line group, the gate of the first transistor and the gate of the second transistor are adjacent to a same insulating layer as the gate metal layer;
• and the data line group, the source and drain of the first transistor and the source and drain of the second transistor are all in the source/drain metal layer;
• and
• the first electrode of the first capacitor is in the gate metal layer and the electrode array layer, and the second electrode of the first capacitor is in the source/drain metal layer.