Compiler configurable to generate instructions executable by different deep learning accelerators from a description of an artificial neural network

A computing device, comprising:

• memory;
• and
• at least one microprocessor configured to:
• receive data representative of a description of an artificial neural network;
• generate a first result of compilation from the data representative of the description of the artificial neural network according to a capability of a first device, the first result including first data representative of first instructions executable on the first device to implement matrix computations of the artificial neural network in accordance with a specification of the first device;
• and
• map an instruction executable by the first device in the first result of compilation into a routine executable by a second device in a second result according to a capability of the second device that is different from the capability of the first device, wherein the routine is configured to pre-optimize performance of a task defined by a combination of instructions executable by the first device, the second result including second data representative of second instructions executable on the second device to implement matrix computations of the artificial neural network.

A non-transitory computer storage medium storing instructions which when executed by a computing device cause the computing device to perform a method, the method comprising:

• receiving, in the computing device, data representative of a description of an artificial neural network;
• generating, by the computing device, a first result of compilation from the data representative of the description of the artificial neural network according to a capability of a first device, the first result including first data representative of first instructions executable on the first device to implement matrix computations of the artificial neural network in accordance with a specification of the first device;
• and
• mapping, by the computing device, an instruction executable by the first device in the first result of compilation into a routine executable by a second device in a second result according to a capability of the second device that is different from the capability of the first device, wherein the routine is configured to pre-optimize performance of a task defined by a combination of instructions executable by the first device, the second result including second data representative of second instructions executable on the second device to implement matrix computations of the artificial neural network;
• wherein the second device includes a Field-Programmable Gate Array (FPGA) or Application Specific Integrated circuit (ASIC) having at least one processing unit operable to execute instructions having matrix operands to implement matrix computations of artificial neural networks.