Data processing engine tile architecture for an integrated circuit

An integrated circuit (IC), comprising:

• a data processing engine (DPE) array having a plurality of DPEs, each DPE of the DPEs comprising:
• a core disposed in a first tile in the DPE array and including compute circuitry and a program memory, the compute circuitry coupled to a stall circuit having a first input coupled to arbitration logic and configured to receive a signal indicative of a memory collision, a second input coupled to a processor subsystem and configured to receive a control signal used to stall the compute circuitry, and a third input coupled to a stream switch and configured to receive signals indicative of an empty or full condition of first-in-first-out (FIFO) circuits;
• a memory circuit disposed in the first tile but to the core, the memory circuit comprising:
• a data memory comprising one or more memory banks;
• a first interface directly connected to the core;
• a second interface directly connected to a respective at least one additional core of a different DPE of the DPE array, wherein the additional core is in a second tile of the DPE array;
• hardware lock circuitry coupled to the data memory and configured to lock memory of the one or more memory banks for access by a selected circuit;
• and
• direct memory access (DMA) circuitry coupled to the data memory;
• a streaming interconnect coupled to the DMA circuitry and the core;
• and
• a memory-mapped interconnect coupled to the core and the memory circuit.

An integrated circuit comprising:

• a data processing engine (DPE) array comprising DPEs, each DPE of the DPEs comprising:
• a core disposed in a first tile in the DPE array and including compute circuitry coupled to a stall circuit having a first input coupled to arbitration logic and configured to receive a signal indicative of a memory collision, a second input coupled to a processor subsystem and configured to receive a control signal used to stall the compute circuitry, and a third input coupled to a stream switch and configured to receive signals indicative of an empty or full condition of first-in-first-out (FIFO) circuits;
• a memory circuit disposed in the first tile but external to the core, the memory circuit comprising memory, a first memory interface, a second memory interface, and direct memory access (DMA) circuitry, the first memory interface being directly connected to the core, the second memory interface being directly connected to an additional core of a neighboring DPE of the DPEs, wherein the additional core is in a second tile of the DPE array;
• the stream switch coupled to the DMA circuitry, the stream switch including one or more configuration registers, the one or more configuration registers being operable to store configuration data to configure the stream switch;
• and
• a memory-mapped switch coupled to the core, the memory circuit, and the one or more configuration registers of the stream switch, the one or more configuration registers being writeable by one or more transactions via the memory-mapped switch;
• and
• wherein:
• the stream switches of the DPEs are coupled together;
• and
• the memory-mapped switches of the DPEs are coupled together.