Processor for configurable parallel computations

A processor receiving a system input data stream, the processor being included in a system that further comprises a host processor, the processor comprising:

• a data bus configured for receiving real time data, wherein at least a portion of the system input data stream is received over the data bus;
• a plurality of stream processors each configurable by the host processor to receive an input data stream and to provide an output data stream, wherein (i) the input data streams of selected one or more of the stream processors receive the system input data stream, and (ii) the stream processors each comprise an instruction memory, a plurality of arithmetic logic circuits, a processor bus and a processing unit, wherein (a) the instruction memory is configurable by the host processor to hold a sequence of instructions executable by the processing unit;
• (b) the processing unit executes the sequence of instructions in its instruction memory to control operations in the arithmetic logic circuits;
• and (c) each arithmetic logic circuit is individually memory-mapped for enablement to allow the arithmetic logic circuits to be enabled in a predetermined order over the processor bus by the host processor or the processing unit;
• and
• a plurality of configurable interconnection circuits connecting the stream processors, each configurable interconnection circuits being configurable by the host processor and one or more of the processing units to selectively route the output data streams of the stream processors as input data streams of the stream processors, wherein the processing units configure the configurable interconnection circuits in the course of executing the sequences of instructions in their instruction memories.