US 12,536,056 B2Granted

Hardware accelerated synchronization with asynchronous transaction support

AssigneeNVIDIA Corporation

InventorsTimothy Guo, Jack Choquette, Shirish Gadre, Olivier Giroux, Harold Carter Edwards, John Edmondson, Manan Patel, Raghavan Madhavan, Jessie Huang, Peter Nelson, Ronny Krashinsky

Life of this patent

Estimating the term…

patentgrep

Loading patent…

Abstract

A new transaction barrier synchronization primitive enables executing threads and asynchronous transactions to synchronize across parallel processors. The asynchronous transactions may include transactions resulting from, for example, hardware data movement units such as direct memory units, etc. A hardware synchronization circuit may provide for the synchronization primitive to be stored in a cache memory so that barrier operations may be accelerated by the circuit. A new wait mechanism reduces software overhead associated with waiting on a barrier.

Claims28

Dependent claims

A synchronization barrier unit comprising:

a cache configured to store, in a cache line, a synchronization barrier retrieved from an address in a memory, wherein the synchronization barrier stored in the cache line comprises at least a tag derived based on the address at which the synchronization barrier is stored in the memory, a thread arrive counter updated in response to thread arrive operations and a transaction counter updated in response to asynchronous transaction operations;
and
a circuit connected to the cache and configured to synchronize a plurality of threads and at least one asynchronous transaction based on the synchronization barrier stored in the cache, wherein the circuit comprises hardware circuitry to update the thread arrive counter in response to the thread arrive operations and to update the transaction counter in response to the asynchronous transaction operations,
wherein the synchronization barrier is configured to be located in a level 2 cache memory.

1 more element

A system comprising:

a plurality of layer 2 (L2) cache memories;
a plurality of processors, each connected to at least one L2 cache memory of the plurality of L2 cache memories;
one or more interconnects connecting the plurality of L2 cache memories and the plurality of processors;
and
a synchronization unit located in one of the processors or one of the L2 cache memories, wherein the synchronization unit comprises:
a cache configured to store, in a cache line, a synchronization barrier retrieved from an address in a memory, wherein the synchronization barrier stored in the cache line comprises at least a tag derived based on the address at which the synchronization barrier is stored in the memory, a thread arrive counter updated in response to thread arrive operations and a transaction counter updated in response to asynchronous transaction operations;
and
a circuit connected to the cache and configured to synchronize a plurality of threads and at least one asynchronous transaction based on the synchronization barrier stored in the cache, wherein the circuit comprises hardware circuitry to update the thread arrive counter in response to the thread arrive operations and to update the transaction counter in response to the asynchronous transaction operations.

5 more elements

Dependencies are inferred from the claim text.