Method and system for predicting branch instructions

A system for predicting branch instructions, wherein the system is adapted to a processor, the processor executes a plurality of instructions that are in a series by using a pipelined architecture, and the plurality of instructions respectively have a plurality of program counter (PC) values, and wherein the pipelined architecture includes a first instruction fetch stage and a second instruction fetch stage;

• and the system comprises:
• a branch predictor including a branch target buffer, wherein the branch target buffer stores a plurality of reference PC values and a plurality of prediction target addresses that respectively correspond to the plurality of reference PC values;
• wherein the branch predictor is configured to execute steps as follows:
• when a first instruction of the plurality of instructions enters the first instruction fetch stage, reading the branch target buffer, and determining whether or not a PC value of the first instruction matches with one of the plurality of reference PC values, wherein the plurality of reference PC values stored in the branch target buffer include a plurality of history PC values of a plurality of history instructions that are executed before the branch instructions, and the plurality of prediction target addresses corresponding to the plurality of history PC values are a plurality of target addresses of the branch instructions, respectively;
• and
• when the first instruction enters the second instruction fetch stage, in response to the PC value of the first instruction matching with one of the plurality of reference PC values, performing a branch prediction according to a prediction counter value, and, in response to a result of the branch prediction being that a branch instruction is taken, selecting a branch target address according to the plurality of prediction target addresses stored in the branch target buffer;
• wherein the branch target buffer further stores a plurality of flag values corresponding to the plurality of reference PC values, and each of the plurality of flag values indicates whether or not a corresponding one of the plurality of reference PC values is one of the plurality of history PC values;
• wherein the branch predictor further includes a comparator circuit, and the step of determining whether or not the PC value of the first instruction matches with one of the plurality of reference PC values further includes:
• inputting the plurality of flag values, the plurality of reference PC values, a sequential state value of the first instruction, and the PC value into the comparator circuit to determine whether or not the PC value of the first instruction matches with one of the plurality of reference PC values and determine whether or not the PC value of the first instruction is sequential, wherein the sequential state value of the first instruction is used to indicate whether or not the first instruction has a jump case before entering the first instruction fetch stage.