Preemptive stoppage of design clocks for processing blocking direct programming interface calls

A non-transitory computer readable medium comprising stored instructions, which when executed by a processor of an emulation system, cause the emulation system to:

• receive, at a first field programable gate array (FPGA) of a plurality of FPGAs of the emulation system, a blocking task at a system clock cycle, K, of a system clock of the emulation system;
• prior to the first FPGA calling the blocking task,
• determine an amount of delay, N, associated with the blocking task, and
• perform operations to communicate a stop clock instruction to each of a set of FPGAs of the plurality of FPGAs such that design clocks of each of the set of FPGAs are stopped in unison at a system clock cycle of K+N, and
• call the blocking task at a system clock cycle of K+N+1.

An emulation system comprising:

• a plurality of field programable gate arrays (FPGAs) that includes a first FPGA and a second FPGA;
• a system clock;
• a memory storing instructions;
• and
• a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the emulation system to:
• receive, at the first FPGA, a blocking direct programming interface (DPI) call at a system clock cycle, K, of the system clock,
• prior to the first FPGA calling the blocking DPI call,
• determine an amount of delay, N, associated with the blocking DPI call, and
• perform operations to communicate a stop clock instruction to the second FPGA such that a design clock of the second FPGA is configured to stop at a clock cycle of K+N, and
• call the blocking DPI call at a system clock cycle of K+N+1.