Method for testing power leakage of circuit and processing system using same

A method for testing power leakage of a circuit, the method comprising:

• obtaining a plurality of undefined nets according to a netlist and power mode information, wherein the power mode information comprises a plurality of power modes, a plurality of power domains, and a plurality of domain modes;
• in each power mode, each power domain corresponds to one domain mode;
• the domain mode is a power-off mode or a power-on mode, the power domains corresponding to the domain modes comprise a power-on domain and a power-off domain, and each undefined net is a circuit connecting line across two power domains;
• obtaining a plurality of trace paths according to one of the undefined nets and the power modes, wherein each trace path is connected to the power-on domain and the power-off domain;
• and
• determining whether there is a risk of power leakage in the each trace path and the power-on domain connected to the each trace path, and outputting a testing result.