US 12,535,525 B2Granted

Interface/unicast for test content, firmware, and software delivery

AssigneeAltera Corporation

InventorsRakesh Kandula, Sankaran Menon, Seng Choon Thor, Shivaprashant Bulusu, Eswar Vadlamani, Ramakrishnan Venkatasubramanian

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Abstract

Techniques for interface conversion and unicast for test content, firmware, and software delivery are described. An example apparatus comprises a scan test interface coupled to multiple circuits blocks to perform a scan test for the multiple circuit blocks, and circuitry coupled to input/output (IO) signals of the scan test interface to provide content for the multiple circuit blocks and to deliver a replicated content to multiple endpoints of the multiple circuit blocks (e.g., unicast technology). In another example, the circuitry is coupled to the IO signals of the scan test interface and a system/communication interface to decode packets received at the IO signals and convert the decoded packets to provide content through the system/communication interface for the multiple circuit blocks. Other examples are described and claimed.

Claims21

Dependent claims

An apparatus comprising:

two or more circuit blocks;
a scan test interface coupled to two or more circuit blocks comprising respective endpoints, the scan test interface comprising one or more input/output (IO) contacts by which the apparatus is to be coupled to a tester device, wherein the scan test interface is to receive scan test data from the tester device with each of the one or more IO contacts, and wherein the scan test interface is to perform a scan test of the two or more circuit blocks with the scan test data;
and
circuitry coupled to the scan test interface, wherein the scan test interface is further to receive first packetized data with each of the one or more IO contacts, and wherein the circuitry is to:
receive the first packetized data via the scan test interface;
replicate the first packetized data to generate second packetized data, comprising the circuitry to generate a first plurality of packets each based on a first packet of the first packetized data;
and
provide packets of the second packetized data each to a different respective circuit block of the two or more circuit blocks;
wherein:
multiple addresses each correspond to a different respective endpoint of the respective endpoints of the two or more circuit blocks;
and
the circuitry to generate the first plurality of packets comprises the circuitry to determine respective addresses of the first plurality of packets each based on both:
an offset address to be communicated to the circuitry via the one or more IO contacts;
and
a different respective one of the multiple addresses.

12 more elements

A method comprising:

providing a scan test interface which is coupled to two or more circuit blocks comprising respective endpoints, the scan test interface comprising one or more input/output (IO) contacts;
receiving scan test data from a tester device with each of the one or more IO contacts;
performing a scan test of the two or more circuit blocks with the scan test interface based on the scan test data;
receiving first packetized data with each of the one or more IO contacts;
replicating the first packetized data to generate second packetized data, comprising generating a first plurality of packets each based on a first packet of the first packetized data;
and
provide packets of the second packetized data each to a different respective circuit block of the two or more circuit blocks;
wherein:
multiple addresses each correspond to a different respective endpoint of the respective endpoints of the two or more circuit blocks;
and
generating the first plurality of packets comprises determining respective addresses of the first plurality of packets each based on both:
an offset address communicated via the one or more IO contacts of the scan test interface;
and
a different respective one of the multiple addresses.

11 more elements

An apparatus comprising:

two or more circuit blocks comprising respective endpoints;
a first interface coupled to the two or more circuit blocks, the first interface comprising one or more input/output (IO) contacts by which the apparatus is to be coupled to a tester device, wherein the first interface is to receive scan test data from the tester device with each of the one or more IO contacts, and wherein the first interface is to perform a scan test of the two or more circuit blocks with the scan test data;
circuitry coupled to the first interface, wherein the first interface is further to receive first packetized data with each of the one or more IO contacts, and wherein the circuitry is to:
receive the first packetized data via the first interface;
replicate the first packetized data to generate second packetized data, comprising the circuitry to generate a first plurality of packets each based on a first packet of the first packetized data;
receive third packetized data with each of the one or more IO contacts of the first interface;
replicate the third packetized data to generate fourth packetized data, comprising the circuitry to generate a second plurality of packets each based on a second packet of the third packetized data;
and
provide packets of the second packetized data each to a different respective circuit block of the two or more circuit blocks;
and
a second interface coupled to the circuitry, the second interface to provide packets of the fourth packetized data each to a different respective circuit block of the two or more circuit blocks;
wherein:
multiple addresses each correspond to a different respective endpoint of the respective endpoints of the two or more circuit blocks;
and
the circuitry to generate the first plurality of packets comprises the circuitry to determine respective addresses of the first plurality of packets each based on both:
an offset address to be communicated to the circuitry via the one or more IO contacts of the first interface;
and
a different respective one of the multiple addresses.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/841,391Filed 15 Jun 2022
Published: US 2023/0408581 A121 Dec 2023
Granted: 27 Jan 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G01R 31/318536
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: scan chain arrangements, e.g. connections, test bus, analog signals
G01R 31/318544
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: scanning methods, algorithms and patterns
G01R 31/318555
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: control logic
G01R 31/318561
Addressing or selecting of subparts of the device under test: identification of the subpart