US 12,532,725 B2Granted

Package structure

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsTung-Liang Shao, Wen-Lin Shih, Su-Chun Yang, Chih-Hang Tung, Chen-Hua Yu

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Abstract

A package structure is provided. The package structure includes a first interconnect structure formed over a first substrate. The package structure also includes a second interconnect structure formed below a second substrate. The package structure further includes a bonding structure between the first interconnect structure and the second interconnect structure. In addition, the bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC). The bonding structure also includes an underfill layer surrounding the bonding structure. A width of the first IMC is greater than a width of the second IMC, and the underfill layer covers a sidewall of the first IMC and a sidewall of the second IMC.

Claims20

Dependent claims

A package structure, comprising:

a first interconnect structure formed over a first substrate;
a second interconnect structure formed below a second substrate;
a bonding structure between the first interconnect structure and the second interconnect structure, wherein the bonding structure comprises a first intermetallic compound (IMC) and a second intermetallic compound (IMC);
a first barrier layer between the first IMC and the first interconnect structure;
a second barrier layer between the second IMC and the second interconnect structure;
and
an underfill layer surrounding the bonding structure, the first barrier layer and the second barrier layer,
wherein a width of the first IMC is greater than a width of the second IMC, wherein the first IMC has a top surface facing the second IMC and opposite sidewalls connected to the top surface, and a portion of the top surface of the first IMC facing the second IMC and the opposite sidewalls of the first IMC are in direct contact with the underfill layer, wherein a maximum lateral width of the first barrier layer is greater than a maximum lateral width of the second barrier layer,
wherein a portion of the underfill layer is laterally sandwiched between the first IMC and the second IMC, wherein a curved interface continuously extends from between the first IMC and the second IMC to beyond opposite sidewalls of the second IMC.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/402,920Filed 16 Aug 2021 · division
Priority: 18 Sep 2018
Published: US 2021/0375724 A12 Dec 2021
Granted: 20 Jan 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification47 codes

H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
H10W 20/023
Of interconnections within wafers or substrates: the interconnections being through-semiconductor vias
H10W 20/0245
The interconnections being through-semiconductor vias: comprising use of blind vias during the manufacture
H10W 20/043
The barrier, adhesion or liner layers being seed or nucleation layers: for electroplating

Family

Application62/732,652Us provisional application · filed 18 Sep 2018
Application16/373,915Parent of this division · filed 3 Apr 2019
US 2021/0375724 A1Pre-grant publication · published 2 Dec 2021
US 11,101,195 B2Parent of this division
US 2020/0091039 A1Published application
US 12,532,725 B2This patent

From the US filing history. Foreign family members aren’t listed.