Transistor arrays with controllable gate voltage

A structure comprising:

• a substrate;
• a dielectric layer on the substrate;
• a first field-effect transistor including a first semiconductor layer over the dielectric layer and a first gate electrode;
• a second field-effect transistor including a second semiconductor layer over the dielectric layer and a second gate electrode adjacent to the first gate electrode, the second semiconductor layer adjoining the first semiconductor layer along an interface;
• and
• a well in the substrate beneath the first field-effect transistor and the second field-effect transistor,
• wherein the dielectric layer is positioned between the well and the first semiconductor layer, and the dielectric layer is positioned between the well and the second semiconductor layer.

A structure comprising:

• a substrate;
• a dielectric layer on the substrate;
• a first field-effect transistor including a first semiconductor layer over the dielectric layer and a first gate electrode;
• a second field-effect transistor including a second semiconductor layer over the dielectric layer and a second gate electrode adjacent to the first gate electrode, the second semiconductor layer electrically connected to the first semiconductor layer;
• and
• a well in the substrate beneath the first field-effect transistor and the second field-effect transistor,
• wherein the dielectric layer is positioned between the well and the first semiconductor layer, and the dielectric layer is positioned between the well and the second semiconductor layer, the first field-effect transistor includes a third semiconductor layer between the first semiconductor layer and the dielectric layer, and the second field-effect transistor includes a fourth semiconductor layer between the second semiconductor layer and the dielectric layer.