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US 12,532,531 B2Granted
Integrated circuit metal gate structure and method of fabricating thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYong-Tian Hou, Yuan-Shun Chao, Chien-Hao Chen, Cheng-Lung Hung
Life of this patent
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Abstract
A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.
Claims18
A method of fabricating a gate for a semiconductor device, comprising:
- depositing a gate dielectric layer;
- forming a gate electrode on the gate dielectric layer, wherein the forming the gate electrode includes:
- depositing a first layer over the gate dielectric layer, wherein the depositing the first layer includes depositing one of titanium nitride (TiN), titanium silicon nitride (TiSiN), or tantalum carbide (TaC);
- depositing a second layer includes depositing a first composition selected from the group consisting of titanium oxynitride (TION), oxidized carbon tantalum (TaCO), oxidized tantalum carbonitride (TaCNO), and combinations thereof, wherein the first layer and the second layer share a first physical interface between the first composition of the second layer and the first layer, and wherein the second layer is directly on and directly contacting the gate dielectric layer such that the first composition physically touches the gate dielectric layer to form a second interface between the first composition of the second layer and the gate dielectric layer;
- diffusing oxygen from the second layer to the gate dielectric layer through the interface;
- and
- after the diffusing, depositing a third layer over the first layer and the second layer, wherein the depositing the third layer includes depositing a nitride of one of tantalum or titanium, wherein the first layer, the second layer, and the third layer form a stack of the gate electrode;
- and
- forming gate spacers abutting the stack of the gate electrode.
6 more elements
A method of fabricating a gate for a semiconductor device, comprising:
- depositing a gate dielectric layer of a gate structure:
- forming a gate electrode of the gate structure on the gate dielectric layer, wherein the forming the gate electrode includes:
- depositing a first layer over the gate dielectric layer, wherein the depositing the first layer includes depositing a first composition of one of titanium nitride (TiN), titanium silicon nitride (TiSiN), or tantalum carbide (TaC);
- depositing a second layer over the gate dielectric layer, wherein the depositing the second layer includes forming a second composition selected from the group consisting of titanium oxynitride (TION), oxidized carbon tantalum (TaCO), oxidized tantalum carbonitride (TaCNO), and combinations thereof, wherein after the depositing the first layer and the depositing the second layer, the second composition of the second layer directly contacts the first composition of the first layer to form a first interface between the second composition of the second layer and the first layer by depositing the first layer directly on a top surface of the second layer, the first interface extending parallel a top surface of the gate dielectric layer, and wherein after the depositing the second layer, the second composition of the second layer directly contacts a top surface of the gate dielectric layer of the gate structure;
- and
- depositing a third layer over the first layer and the second layer, wherein the depositing the third layer includes depositing a nitride of one of tantalum or titanium;
- wherein the gate electrode comprises the deposited first layer, the deposited second layer, and the deposited the third layer.
4 more elements
A method of fabricating a semiconductor device, comprising:
- forming a gate dielectric layer;
- providing a gate electrode on the gate dielectric layer, wherein the providing the gate electrode includes:
- forming a first layer over the gate dielectric layer, wherein the first layer includes one of titanium nitride (TiN), titanium silicon nitride (TiSiN), or tantalum carbide (TaC);
- forming a second layer over the gate dielectric layer, wherein the second layer includes metal and oxygen, wherein the second layer includes a composition selected from the group consisting of titanium oxynitride (TION), oxidized carbon tantalum (TaCO), oxidized tantalum carbonitride (TaCNO), or combinations thereof, wherein the second layer directly contacts the gate dielectric layer, and wherein the first layer and the second layer share an interface;
- and
- forming a third layer including metal nitride of one of tantalum or titanium vertically over the second layer, wherein the first layer, the second layer, and the third layer form a multi-layer metal gate for a single transistor.
3 more elements
Dependencies are inferred from the claim text.