Method of forming top select gate trenches

A method for fabricating a semiconductor device, comprising:

• forming a first dielectric trench in a core region of a first stack of alternating insulating layers and sacrificial word line layers, the first stack arranged over a substrate and including the core region and a staircase region;
• forming a second dielectric trench, adjacent to and connected with the first dielectric trench, in the staircase region of the first stack;
• forming dummy channel structures extending through the first stack, the dummy channel structures being spaced apart from the second dielectric trench;
• forming a gate line cut trench that extend through the first stack, the gate line cut trench extending in a same direction as the first dielectric trench and the second dielectric trench and dividing the first stack into first substacks;
• and
• replacing the sacrificial word line layer with word line layers.

A method for fabricating a semiconductor device, comprising:

• forming a first dielectric trench in a core region of a first stack of alternating insulating layers and sacrificial word line layers, the first stack arranged over a substrate and including the core region and a staircase region;
• forming a second dielectric trench, adjacent to and connected with the first dielectric trench, in the staircase region of the first stack;
• and
• forming dummy channel structures extending through the first stack, the dummy channel structures being spaced apart from the second dielectric trench,
• wherein the first dielectric trench and the second dielectric trench extend through a topmost sacrificial word line layer (TSWLL) of the first stack and divide the TSWLL into sub-TSWLLs.