Input capacitance enhancement for ESD ruggedness in semiconductor devices

A semiconductor die, comprising:

• a semiconductor substrate;
• a power transistor formed in a first region of the semiconductor substrate and including a plurality of gate trenches in the first region, the plurality of gate trenches including gate electrodes that are capacitively coupled to the semiconductor substrate and contribute to an input capacitance of the power transistor;
• a gate pad formed over a second region of the semiconductor substrate that is devoid of functional transistor cells;
• and
• a plurality of additional gate trenches formed in the second region, the plurality of additional gate trenches including additional gate electrodes that are capacitively coupled to the semiconductor substrate and increase the input capacitance of the power transistor,
• wherein in the second region, the plurality of additional gate trenches terminates in a doped region having a same conductivity type as a body region of the power transistor and a gate dielectric separates the additional gate electrodes from the doped region.

A method of producing a semiconductor die, the method comprising:

• forming a plurality of transistor cells in a first region of a semiconductor substrate, the plurality of transistor cells being electrically coupled in parallel to form a power transistor and including first trenches that extend from a first surface of the semiconductor substrate into the first region;
• forming a gate pad above the first surface and over a second region of the semiconductor substrate that is devoid of functional transistor cells, the gate pad being electrically connected to gate electrodes in the first trenches;
• forming a plurality of second trenches extending from the first surface into the second region, the plurality of second trenches including gate electrodes that are electrically connected to the gate pad and form a first conductor of an additional input capacitance of the power transistor;
• and
• forming a second conductor of the additional input capacitance in the second region adjacent the plurality of second trenches,
• wherein in the second region, the plurality of second trenches terminates in a doped region having a same conductivity type as a body region of the plurality of transistor cells and a gate dielectric separates the gate electrodes in the second trenches from the doped region.