Three-dimensional (3D) semiconductor memory device including a separation structure and electronic system including the same

A three-dimensional (3D) semiconductor memory device comprising:

• a substrate;
• a stack structure comprising interlayer dielectric layers and gate electrodes which are alternately and repeatedly stacked on the substrate;
• vertical channel structures in vertical channel holes penetrating the stack structure;
• a separation structure spaced apart from the vertical channel structures and filling a trench crossing the stack structure, the separation structure comprising a spacer covering an inner sidewall of the trench, and a first conductive contact filling an inner space of the trench surrounded by the spacer;
• a common source region vertically overlapping with the separation structure and in an upper portion of the substrate;
• an insulating layer covering the substrate and the stack structure;
• a second conductive contact spaced apart from the stack structure and penetrating the insulating layer so as to be connected to a peripheral circuit transistor;
• a first contact plug penetrating the insulating layer so as to be in contact with the first conductive contact of the separation structure;
• second contact plugs penetrating the insulating layer and at least a portion of the stack structure so as to be connected to the gate electrodes;
• and
• a third contact plug penetrating the insulating layer so as to be in contact with the second conductive contact,
• wherein a top surface of the first conductive contact and a top surface of the second conductive contact are at a level lower than top surfaces of the first contact plug, the second contact plugs, and the third contact plugs and higher than top surfaces of the vertical channel structures, and
• wherein a bottommost surface of the first conductive contact is at a level lower than a bottommost surface of the spacer, the bottommost surface of the first conductive contact is at a level lower than a bottommost surface of the vertical channel structures,
• wherein the spacer comprises:
• a first spacer covering the inner sidewall of the trench and a portion of a bottom surface of the trench;
• and
• a second spacer disposed between the first spacer and the first conductive contact,
• wherein the second spacer is spaced apart from the common source region with a portion of the first spacer interposed therebetween,
• wherein the top surface of the first contact plug and the top surface of the third contact plug are coplanar with each other
• wherein a bottommost surface of the first spacer is at a level lower than a bottommost surface of the second spacer, and
• wherein the bottommost surface of the second spacer is at a level lower than a topmost surface of the substrate.

An electronic system comprising:

• a three-dimensional (3D) semiconductor memory device comprising a first substrate, a peripheral circuit structure on the first substrate, a cell array structure on the peripheral circuit structure, an insulating layer covering the cell array structure, and an input/output pad on the insulating layer and electrically connected to the peripheral circuit structure;
• and
• a controller electrically connected to the 3D semiconductor memory device through the input/output pad and configured to control the 3D semiconductor memory device,
• wherein the cell array structure comprises:
• a second substrate on the peripheral circuit structure;
• a stack structure comprising interlayer dielectric layers and gate electrodes which are alternately and repeatedly stacked on the second substrate;
• vertical channel structures penetrating the stack structure;
• a separation structure spaced apart from the vertical channel structures and filling a trench crossing the stack structure, the separation structure comprising a spacer covering an inner sidewall of the trench, and a first conductive contact filling an inner space of the trench surrounded by the spacer;
• contact plugs penetrating the insulating layer so as to be connected to the gate electrodes of the stack structure;
• a second conductive contact spaced apart from the stack structure and penetrating the insulating layer so as to be electrically connected to the peripheral circuit structure;
• and
• a common source region vertically overlapping with the separation structure and in an upper portion of the second substrate,
• wherein a bottommost surface of the first conductive contact is at a level lower than a bottommost surface of the spacer, the bottommost surface of the first conductive contact is at a level lower than a bottommost surface of the vertical channel structures and a topmost surface of the second substrate, and
• wherein the common source region covers the bottommost surface of the first conductive contact and a portion of sidewalls of the first conductive contact,
• wherein the spacer comprises:
• a first spacer covering the inner sidewall of the trench;
• and
• a second spacer between the first spacer and the first conductive contact,
• wherein a bottommost surface of the first spacer is at a level lower than a bottommost surface of the second spacer, and
• wherein the bottommost surface of the second spacer is at a level lower than the topmost surface of the second substrate.