Semiconductor structure and manufacturing method thereof

A semiconductor structure, comprising:

• a substrate and a stacked structure located on the substrate;
• a doped region located between the stacked structure and the substrate, wherein on a section perpendicular to the substrate, the doped region comprises a top doped region, a bottom doped region, and an intermediate doped region connecting the top doped region to the bottom doped region, in a direction parallel to the substrate, the top doped region has a first width, the bottom doped region has a second width, the intermediate doped region has a gradually changing third width, the first width is greater than the second width, and the gradually changing third width decreases gradually along a direction away from the substrate;
• wherein the stacked structure comprises a gate stack structure, the gate stack structure comprises a gate dielectric layer in contact with the doped region, and a first gate conductive layer and a second gate conductive layer on the gate dielectric layer, and on the section perpendicular to the substrate, the first gate conductive layer is thinner than the second gate conductive layer;
• and
• the stacked structure further comprises a dielectric stack structure on the top doped region, the gate stack structure is located on the intermediate doped region and the bottom doped region, and a top surface of the dielectric stack structure is higher than a top surface of the gate stack structure.