Apparatus and method for low density parity check code decoding
AssigneeNokia Solutions and Networks Oy
InventorsYannick Lefevre, Paul Cautereels
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Abstract
Apparatus and method for low density parity check code decoding in a first processing device, wherein the method includes receiving a first bit-word of a first length related to a log-likelihood ratio of a bit of a signal; obtaining a second bit-word of a second length that is shorter than the first length, wherein obtaining the second bit-word comprises applying a correction to the first bit-word; and determining a message depending on a set of second bit-words, wherein the set of second bit-words includes the second bit-word.
Claims11
A method for use in low density parity check code decoding with a min-sum decoder, wherein the method comprises:
- receiving a first bit-word of a first length related to a log-likelihood ratio of a bit of a signal;
- obtaining a second bit-word of a second length that is shorter than the first length, wherein obtaining the second bit-word comprises applying a correction to the first bit-word;
- determining a message depending on a set of second bit-words according to a configuration provided by a parity check matrix, wherein the set of second bit-words includes the second bit-word;
- determining a sign of the message depending on a product of signs of second bit-words in the set of second bit-words;
- and
- determining a magnitude of the message depending on a smallest magnitude of the second bit-words in the set of second bit-words.
An apparatus for low density parity check code decoding with a min-sum decoder, wherein the apparatus comprises:
- a non-transitory computer readable medium storing instructions;
- and
- at least one processor configured to execute the instructions to cause the apparatus to perform,
- receiving a first bit-word of a first length related to a log-likelihood ratio of a bit of a signal;
- obtaining a second bit-word of a second length that is shorter than the first length, wherein obtaining the second bit-word includes applying a correction to the first bit-word;
- determining a message depending on a set of second bit-words according to a configuration provided by a parity check matrix, wherein the set of second bit-words includes the second bit-word;
- determining a sign of the message depending on a product of signs of second bit-words in the set of second bit-words;
- and
- determining a magnitude of the message depending on a smallest magnitude of the second bit-words in the set of second bit-words.
A non-transitory computer readable medium comprising program instructions, which when executed by at least one processor, causes an apparatus including the at least one processor to perform a method for use in low density parity check code decoding with a min sum decoder, the method comprising:
- receiving a first bit-word of a first length related to a log-likelihood ratio of a bit of a signal;
- obtaining a second bit-word of a second length that is shorter than the first length, wherein obtaining the second bit-word includes applying a correction to the first bit-word;
- determining a message depending on a set of second bit-words according to a configuration provided by a parity check matrix, wherein the set of second bit-words includes the second bit-word;
- determining a sign of the message depending on a product of signs of second bit-words in the set of second bit-words;
- and
- determining a magnitude of the message depending on a smallest magnitude of the second bit-words in the set of second bit-words.
Dependencies are inferred from the claim text.