Error correction decoding device

A decoding device comprising:

• processing circuitry configured to:
• perform an initialization process on a storage element for likelihood information to be used in likelihood calculation of an iterative decoding process on a basis of likelihood information to be input and a code length of a bit sequence to be decoded;
• execute M separate first likelihood calculations corresponding to step 1 to step M where M is an integer of 2 or more, in likelihood calculation of the iterative decoding process;
• execute M separate second likelihood calculations corresponding to step M+1 to step 2M in likelihood calculation of the iterative decoding process;
• make a hard decision on a result of likelihood calculation and to generate a decoded bit sequence;
• remove a frozen bit and a bit sequence based on the code length of the bit sequence to be decoded from the decoded bit sequence and to generate a decoded information bit sequence;
• and
• control likelihood calculation of the iterative decoding process on a basis of the code length of the bit sequence to be decoded, wherein
• each of the first likelihood calculations and the second likelihood calculations includes one or more steps,
• the processing circuitry is configured to perform the one or more steps of each of the first likelihood calculations and the second likelihood calculations iteratively,
• Mt is a positive integer less than or equal to the M, and
• the processing circuitry is further configured to perform an iterative decoding process for iteratively executing Mt separate likelihood calculations corresponding to step M+1 to step M+Mt, and a terminal likelihood calculation process for executing M−Mt separate likelihood calculations corresponding to step M+Mt+1 to step 2M.