Circuit arrangement comprising a MOS sensor, in particular TMOS sensor, and a corresponding method for operating the circuit arrangement

A circuit arrangement, comprising:

• a first integrated circuit die comprising:
• a sensor circuit comprising a first FET and a second FET arranged in a differential pair and configured to supply a differential current at a respective first node and a respective second node;
• and
• a circuit configured to switch a sign of said differential current according to a period of complementary phase clock signals to supply a sign switched differential current at a third node and a fourth node;
• a second integrated circuit die comprising:
• an electronic reading circuit comprising a differential current reading circuit including a first input terminal coupled to said third node and a second input terminal coupled to said fourth node, said differential current reading circuit comprising a current to voltage converter coupled to the first and second input terminals and an analog to digital converter coupled to outputs of the current to voltage converter and configured to output a digital signal;
• and
• a circuit configured to operate a selection of signals at its output depending on a value of said period of the complementary phase clock signals, select said sign switched differential current and eliminate spurious currents;
• an ESD protection circuit interposed between at least said third and fourth node of said circuit configured to switch the sign and the first and second input terminals of said differential current reading circuit, wherein said ESD protection circuit comprises diodes applying injection of currents from voltage supply and ground at the third and fourth nodes of the circuit configured to switch the sign and at the first and second input terminals of the differential current reading circuit and adds said spurious currents to said sign switched differential current supplied by the circuit configured to switch the sign;
• and
• a phase clock signal generator generating the complementary phase clock signals, wherein the period corresponds to one of a sampling interval of said analog to digital converter or a multiple of said sampling interval.