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US 12,531,564 B2Granted
Synchronizing multiple phase-locked loop circuits
AssigneeQUALCOMM Incorporated
InventorsJianjun Yu, Tomas O'Sullivan, Razak Hossain, Lai Kan Leung
Life of this patent
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Abstract
Aspects of the present disclosure provide techniques and apparatus for synchronizing phase-locked loop (PLL) circuits. An example method of operating PLL circuits includes obtaining an indication to perform a synchronizing action at a first PLL circuit and a second PLL circuit; and performing the synchronizing action at the first PLL circuit and the second PLL circuit in response to obtaining the indication.
Claims28
A method of operating phase-locked loop (PLL) circuits, comprising:
- obtaining an indication to perform a synchronizing action at a first PLL circuit and a second PLL circuit;
- performing the synchronizing action at the first PLL circuit and the second PLL circuit in response to obtaining the indication by at least one of performing a frequency hop at the first PLL circuit and the second PLL circuit or performing a frequency correction at the first PLL circuit and the second PLL circuit;
- outputting a first signal via a first transmit path having the first PLL circuit;
- and
- outputting a second signal via a second transmit path having the second PLL circuit, such that the first signal is coherent with the second signal.
2 more elements
A method of operating phase-locked loop (PLL) circuits, comprising:
- obtaining an indication to perform a synchronizing action at a first PLL circuit and a second PLL circuit;
- performing the synchronizing action at the first PLL circuit and the second PLL circuit in response to obtaining the indication;
- enabling, at each of the first PLL circuit and the second PLL circuit, a delta sigma modulator (DSM) and phase continuity circuitry to receive a common trigger, wherein the indication to perform the synchronizing action includes the common trigger;
- and
- resetting, at each of the first PLL circuit and the second PLL circuit, the DSM and the phase continuity circuitry, wherein performing the synchronizing action comprises initializing the first PLL circuit and the second PLL circuit in response to obtaining the common trigger.
2 more elements
A method of operating phase-locked loop (PLL) circuits, comprising:
- obtaining an indication to perform a synchronizing action at a first PLL circuit and a second PLL circuit;
- performing the synchronizing action at the first PLL circuit and the second PLL circuit in response to obtaining the indication;
- setting, at each of the first PLL circuit and the second PLL circuit, a state machine to a particular state;
- obtaining, at each of the first PLL circuit and the second PLL circuit, an indication to switch from outputting a first frequency to a second frequency;
- and
- enabling, at each of the first PLL circuit and the second PLL circuit, the state machine to receive a common trigger, wherein the indication to perform the synchronizing action includes the common trigger and wherein performing the synchronizing action comprises performing a frequency hop at the first PLL circuit and the second PLL circuit in response to obtaining the common trigger.
3 more elements
A method of operating phase-locked loop (PLL) circuits, comprising:
- obtaining an indication to perform a synchronizing action at a first PLL circuit and a second PLL circuit;
- performing the synchronizing action at the first PLL circuit and the second PLL circuit in response to obtaining the indication;
- and
- obtaining, at each of the first PLL circuit and the second PLL circuit, an indication to update a base frequency, wherein:
- the indication to perform the synchronizing action includes a frequency correction trigger;
- and
- performing the synchronizing action comprises outputting, from each of the first PLL circuit and the second PLL circuit, a periodic signal at a frequency based on the updated base frequency in response to obtaining the frequency correction trigger.
4 more elements
A method of operating phase-locked loop (PLL) circuits, comprising:
- obtaining an indication to perform a synchronizing action at a first PLL circuit and a second PLL circuit;
- performing the synchronizing action at the first PLL circuit and the second PLL circuit in response to obtaining the indication;
- and
- resetting a reference clock generator coupled to each of the first PLL circuit and the second PLL circuit.
1 more element
An apparatus comprising:
- a first PLL circuit;
- a second PLL circuit,
- a first transmit path having the first PLL circuit, wherein the first transmit path is configured to output a first signal using the first PLL circuit;
- and
- a second transmit path having the second PLL circuit, wherein the second transmit path is configured to output a second signal using the second PLL circuit, such that the first signal is coherent with the second signal, and wherein the first PLL circuit and the second PLL circuit are configured to:
- obtain an indication to perform a synchronizing action, and
- perform the synchronizing action in response to obtaining the indication by at least one of performing a frequency hop at the first PLL circuit and the second PLL circuit or performing a frequency correction at the first PLL circuit and the second PLL circuit.
4 more elements
An apparatus comprising:
- a first PLL circuit;
- and
- a second PLL circuit, wherein the first PLL circuit and the second PLL circuit are configured to:
- obtain an indication to perform a synchronizing action;
- perform the synchronizing action in response to obtaining the indication;
- enable, at each of the first PLL circuit and the second PLL circuit, a delta sigma modulator (DSM) and phase continuity circuitry to receive a common trigger, wherein the indication to perform the synchronizing action includes the common trigger;
- and
- reset, at each of the first PLL circuit and the second PLL circuit, the DSM and the phase continuity circuitry, wherein to perform the synchronizing action, the first PLL circuit and the second PLL circuit are further configured to initialize the first PLL circuit and the second PLL circuit in response to obtaining the common trigger.
5 more elements
An apparatus comprising:
- a first PLL circuit;
- and
- a second PLL circuit, wherein the first PLL circuit and the second PLL circuit are configured to:
- obtain an indication to perform a synchronizing action;
- perform the synchronizing action in response to obtaining the indication;
- set, at each of the first PLL circuit and the second PLL circuit, a state machine to a particular state;
- obtain, at each of the first PLL circuit and the second PLL circuit, an indication to switch from outputting a first frequency to a second frequency;
- and
- enable, at each of the first PLL circuit and the second PLL circuit, the state machine to receive a common trigger, wherein the indication to perform the synchronizing action includes the common trigger and wherein to perform the synchronizing action, the first PLL circuit and the second PLL circuit are further configured to perform a frequency hop at the first PLL circuit and the second PLL circuit in response to obtaining the common trigger.
6 more elements
An apparatus comprising:
- a first PLL circuit;
- and
- a second PLL circuit, wherein the first PLL circuit and the second PLL circuit are configured to:
- obtain an indication to perform a synchronizing action;
- perform the synchronizing action in response to obtaining the indication;
- and
- obtain, at each of the first PLL circuit and the second PLL circuit, an indication to update a base frequency, wherein:
- the indication to perform the synchronizing action includes a frequency correction trigger;
- and
- to perform the synchronizing action, the first PLL circuit and the second PLL circuit are further configured to output, from each of the first PLL circuit and the second PLL circuit, a periodic signal at a frequency based on the updated base frequency in response to obtaining the frequency correction trigger.
7 more elements
An apparatus comprising:
- a first PLL circuit;
- a second PLL circuit, wherein the first PLL circuit and the second PLL circuit are configured to:
- obtain an indication to perform a synchronizing action;
- and
- perform the synchronizing action in response to obtaining the indication;
- a reference clock generator coupled to each of the first PLL circuit and the second PLL circuit;
- memory;
- and
- one or more processors coupled to the memory, wherein the one or more processors are configured to reset the reference clock generator.
6 more elements
Dependencies are inferred from the claim text.