Phase-locked loop control circuit, phase-locked loop circuit and control method thereof

A phase-locked loop (PLL) control circuit for controlling an output clock signal of an oscillation circuit, wherein the PLL control circuit comprises:

• a reference current generation circuit configured to generate a reference current;
• a frequency calibration circuit configured to generate a current adjustment signal according to a target frequency;
• a magnification adjustment circuit configured to adjust the reference current to a target frequency current according to the current adjustment signal, wherein the oscillation circuit generates an output clock signal according to the target frequency current;
• and
• a front-end circuit configured to detect a phase difference and a frequency difference between the output clock signal and a reference clock signal to generate a first control signal for the oscillation circuit to adjust an output frequency of the output clock signal to be the same as the target frequency based on the first control signal and the target frequency current;
• wherein when the first control signal shifts, the front-end circuit is further configured to generate a second control signal for the magnification adjustment circuit to adjust the target frequency current according to a sum of the reference current and the second control signal;
• wherein when the first control signal shifts beyond a control range of the second control signal, the front-end circuit is further configured to generate an upper-limit control signal and a lower-limit control signal for the frequency calibration circuit to generate the corresponding current adjustment signal according to the target frequency, the upper-limit control signal and the lower-limit control signal.

A control method of a phase-locked loop (PLL) circuit for controlling an oscillation circuit, wherein the control method comprises:

• performing a frequency calibration operation, comprising:
• generating a corresponding current adjustment signal to a magnification adjustment circuit according to a target frequency of the oscillation circuit;
• providing a reference current to the magnification adjustment circuit;
• and
• adjusting the reference current to a target frequency current according to the current adjustment signal, so that the oscillation circuit generates an output clock signal according to the target frequency current;
• and
• performing a PLL operation, comprising:
• using a front-end circuit to detect a phase difference and a frequency difference between the output clock signal and a reference clock signal;
• and
• generating a first control signal for the oscillation circuit to adjust an output frequency of the output clock signal to be the same as the target frequency based on the first control signal and the target frequency current;
• wherein when the first control signal shifts, the front-end circuit further generates a second control signal for the magnification adjustment circuit to adjust the target frequency current according to a sum of the reference current and the second control signal.