CMOS circuit
AssigneeJapan Aerospace Exploration Agency
InventorKozo Takeuchi
Life of this patent
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Abstract
A complementary metal oxide semiconductor (CMOS) circuit includes a logical operation circuit formed on a substrate of a first conductivity type and including at least a combination of a first transistor of the first conductivity type having a first well of a second conductivity type different from the first conductivity type and a second transistor of the second conductivity type having a second well of the first conductivity type, a third transistor of the first conductivity type having a gate terminal connected to the second well, and a fourth transistor of the second conductivity type having a gate terminal connected to the first well.
Claims6
A complementary metal oxide semiconductor (CMOS) circuit comprising:
- a logical operation circuit formed on a substrate of a first conductivity type and including at least a combination of a first transistor of the first conductivity type having a first well of a second conductivity type different from the first conductivity type and a second transistor of the second conductivity type having a second well of the first conductivity type;
- a third transistor of the first conductivity type having a gate terminal connected to the second well;
- and
- a fourth transistor of the second conductivity type having a gate terminal connected to the first well,
- wherein the gate terminal of the third transistor is connected to the second well of the second transistor,
- wherein the gate terminal of the fourth transistor is connected to the first well of the first transistor,
- wherein the third transistor has a source terminal fixed to a power-supply potential and a drain terminal connected to a source terminal of the first transistor, and
- wherein the fourth transistor has a source terminal fixed to a ground potential and a drain terminal connected to a source terminal of the second transistor.
A complementary metal oxide semiconductor (CMOS) circuit comprising:
- a logical operation circuit formed on a substrate of a first conductivity type and including at least a combination of a first transistor of the first conductivity type having a first well of a second conductivity type different from the first conductivity type and a second transistor of the second conductivity type having a second well of the first conductivity type;
- a third transistor of the first conductivity type having a gate terminal connected to the second well;
- and
- a fourth transistor of the second conductivity type having a gate terminal connected to the first well,
- wherein the gate terminal of the third transistor is connected to the second well of the second transistor,
- wherein the gate terminal of the fourth transistor is connected to the first well of the first transistor,
- wherein the first transistor has a source terminal fixed to a power-supply potential,
- wherein the third transistor has a source terminal connected to a drain terminal of the first transistor,
- wherein the second transistor has a source terminal fixed to a ground potential,
- wherein the fourth transistor has a source terminal connected to a drain terminal of the second transistor, and
- wherein a drain terminal of the third transistor and a drain terminal of the fourth transistor are connected to an output terminal of the logical operation circuit.
A complementary metal oxide semiconductor (CMOS) circuit comprising:
- a logical operation circuit formed on a substrate of a first conductivity type and including at least a combination of a first transistor of the first conductivity type having a first well of a second conductivity type different from the first conductivity type and a second transistor of the second conductivity type having a second well of the first conductivity type;
- a third transistor of the first conductivity type having a gate terminal connected to the second well;
- and
- a fourth transistor of the second conductivity type having a gate terminal connected to the first well,
- wherein the logical operation circuit is a logical operation circuit including a combination of a plurality of first transistors and a plurality of second transistors, and
- wherein one third transistor and one fourth transistor are provided.
Dependencies are inferred from the claim text.