Current feedback amplifier
AssigneeIntel Corporation
InventorsGiacomo Cascio, Martin Clara, Marc Jan Georges Tiebout, Daniel Gruber
Life of this patent
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Abstract
A current feedback amplifier (CFA). The CFA includes a common-gate input stage, a biasing circuitry, and a differential pair coupled in parallel between the supply voltage node and the reference voltage node. The common-gate input stage amplifies an input signal received at an input node and supplies it to a gate of the complementary transistors of the differential pair. The biasing circuitry supplies a bias voltage to a gate of the transistors of the common-gate input stage. The input node of the common-gate input stage and a node between the complementary transistors in the first path of the differential pair are shorted.
Claims20
A current feedback amplifier, comprising:
- a common-gate input stage comprising a first transistor and a second transistor coupled in series, wherein the common-gate input stage is configured to amplify an input signal received at an input node between the first transistor and the second transistor and generate an output at a first output node between the first transistor and a supply voltage node and a second output node between the second transistor and a reference voltage node;
- a biasing circuitry comprising a third transistor and a fourth transistor coupled in series and configured to supply a bias voltage to a gate of the first transistor and a gate of the second transistor of the common-gate input stage to maintain the first transistor and the second transistor of the common-gate input stage in a conducting state;
- and
- a differential pair comprising a first path and a second path coupled in parallel, each of the first path and the second path of the differential pair comprising a fifth transistor and a sixth transistor coupled in series, wherein the first output node of the common-gate input stage is coupled to a gate of the fifth transistor of the first path of the differential pair and the second output node of the common-gate input stage is coupled to the sixth transistor of the first path of the differential pair and an output is generated at an output node between the fifth and sixth transistors in the second path,
- wherein the common-gate input stage, the differential pair, and the biasing circuitry are coupled in parallel between the supply voltage node and the reference voltage node,
- wherein the input node of the common-gate input stage and a node between the fifth transistor and the sixth transistor in the first path of the differential pair are shorted.
Dependencies are inferred from the claim text.