RF amplifier of accurate bias and healthy headroom and method thereof

A method comprising:

• incorporating a first NMOSFET (n-channel metal oxide semiconductor field effect transistor) as a common-source amplifier;
• incorporating a second NMOSFET as a cascode device stacked upon the first NMOSFET, wherein a source of the second NMOSFET connects to a drain of the first NMOSFET and a drain of the second NMOSFET connects to a power supply node via a load inductor;
• injecting a reference current into a drain of a third NMOSFET;
• using a first operational amplifier to generate a first bias voltage to control a gate of the first NMOSFET, a gate of the third NMOSFET, and a gate of a fourth NMOSFET in accordance with a voltage difference between the drain of the third NMOSFET and either a drain of the fourth NMOSFET or a reference voltage;
• incorporating a fifth NMOSFET stacked upon the fourth NMOSFET, wherein a source of the fifth NMOSFET connects to the drain of the fourth NMOSFET and a drain of the fifth NMOSFET connects to the power supply node;
• and
• using a second operational amplifier to generate a second bias voltage to control both a gate of the second NMOSFET and a gate of the fifth NMOSFET in accordance with a voltage difference between the reference voltage and the drain of the fourth NMOSFET.

A method comprising:

• incorporating a cascode amplifier comprising a second NMOSFET stacked upon a first NMOSFET;
• incorporating a fifth NMOSFET stacked upon a fourth NMOSFET in the same way as the second NMOSFET is stacked upon the first NMOSFET;
• injecting a reference current into a drain of a third NMOSFET;
• configuring the third NMOSFET and the fourth NMOSFET to be a current mirror by using a first bias voltage to control both a gate of the third NMOSFET and a gate of the fourth NMOSFET;
• establishing the first bias voltage in accordance with a voltage difference between the drain of the third NMOSFET and either a drain of the fourth NMOSFET or a reference voltage using a first operational amplifier;
• establishing a second bias voltage to control a gate of the fifth NMOSFET in accordance with a voltage difference between the reference voltage and the drain of the fourth NMOSFET;
• using the first bias voltage to control a gate of the first NMOSFET;
• using the second bias voltage to control of a gate of the second NMOSFET;
• connecting a drain of the fifth NMOSFET to a power supply node;
• and
• connecting a drain of the second NMOSFET to the power supply node via a load inductor.