PLL circuit and method for generating a modulated carrier signal

A method for generating a modulated carrier signal, the method comprising

• providing a controlled oscillator configured to generate a controlled oscillator output signal (CKV) as the modulated carrier signal;
• receiving a desired phase change (ΔϕM[n]) as a modulation signal at an n-th cycle of a non-uniform clock (CKR2) derived from the controlled oscillator output signal (CKV) and a uniform reference clock (FREF) of a PLL circuit;
• providing the desired phase change (ΔϕM[n]) to the controlled oscillator to change its oscillation frequency based on the desired phase change (ΔϕM[n]);
• receiving a frequency control word (FCW) at the n-th cycle of the non-uniform clock (CKR2), the frequency control word (FCW) being a ratio of a desired carrier frequency (fc) of the carrier signal and a frequency (fREF) of the uniform reference clock;
• providing the desired phase change (ΔϕM) to a frequency control word accumulator configured to accumulate the desired phase change (ΔϕM[n]) and the FCW to generate a first phase prediction (ϕR[n]) of the controlled oscillator's output phase at the (n+1)-th cycle of the non-uniform clock (CKR2);
• recursively calculating, using the desired phase change (ΔϕM[n]), the frequency control word FCW, and the first phase prediction (ϕR[n]), a non-uniform clock compensation value (ϕDMC[n]) for the desired phase change ΔϕM[n] on the first path and/or a second phase prediction (ϕS[n]) of the controlled oscillator's output phase at the (n+1)-th cycle of the uniform reference clock (FREF);
• and
• estimating an error between the second phase prediction (ϕS[n]) and an instantaneous time offset (ΔtS) between the uniform reference clock (FREF) and the controlled oscillator output signal (CKV) and generating a control signal for the controlled oscillator based on the estimated error.