US 12,531,513 B2 · Crystal oscillator with on-chip negative resistance margin measurement circuit

Abstract

Embodiments of methods and semiconductor devices are described that are configured to determine a negative resistance margin (NRM) of an oscillator circuit. The semiconductor device may include an integrated circuit including an amplifier circuit coupled between a first node and a second node and NRM test circuitry including a resistor circuit selectively coupled between a first contact pad and the first node. The integrated circuit may receive an oscillating signal from an oscillator circuit coupled to the first contact pad and a second contact pad of the integrated circuit. In an NRM test mode, a resistance of the resistor circuit is selectively varied from an initial resistance value to one or more second resistance values and the oscillating signal is monitored at the second node to determine the NRM based on the one or more second resistance values when an amplitude of the oscillating signal falls below a threshold amplitude.

Claims19

Dependent claims

A method of determining a negative resistance margin (NRM) of an oscillator circuit, the method comprising:

providing an integrated circuit including an amplifier circuit coupled between a first node and a second node, the integrated circuit including NRM test circuitry including a resistor circuit selectively coupled between a first contact pad and the first node;
receiving, at the integrated circuit, an oscillating signal from an oscillator circuit coupled to the first contact pad and a second contact pad of the integrated circuit;
in an NRM test mode, selectively varying a resistance of the resistor circuit from an initial resistance value to one or more second resistance values;
and
monitoring the oscillating signal at the second node to determine the NRM based on the one or more second resistance values when an amplitude of the oscillating signal falls below a threshold amplitude;
and
wherein, in an operating mode, the method comprises selectively enabling a bypass signal path between the first contact pad and the first node to bypass the resistor circuit.

4 more elements

A semiconductor device comprising:

an amplifier circuit coupled between an input node and an output node;
a first contact pad configured to be coupled to an oscillator circuit;
a second contact pad configured to be coupled to the oscillator circuit;
and
negative resistance margin (NRM) test circuitry coupled between the first contact pad and the input node, the NRM test circuitry comprising:
a capacitor circuit selectively coupled to the input node in an NRM test mode and configurable to provide a selected capacitance to the input node to produce a frequency error of zero at the output node;
and
a resistor circuit selectively coupled to the input node in the NRM test mode and configured to provide a tunable resistance that is selectively applied to the input node and incrementally adjusted until an amplitude of oscillations of the oscillator circuit are less than a threshold amplitude indicative of a negative resistance of the amplifier circuit.

5 more elements

Dependencies are inferred from the claim text.

Crystal oscillator with on-chip negative resistance margin measurement circuit

Life of this patent

Crystal oscillator with on-chip negative resistance margin measurement circuit

Life of this patent

Abstract

Claims19