Method and non-transitory computer-readable storage medium and apparatus for executing host commands

A non-transitory computer-readable storage medium having stored therein program code that, when loaded and executed by a processing unit, causes the processing unit to:

• set a first start register and a first end register to store a first logical address range from a first start logical address to a first end logical address for an execution of a host command;
• provide a sequential update queue comprising a plurality of entries, wherein each entry defines a second logical address range from a second start logical address to a second end logical address, and to-be-programmed data of each second logical address range is temporarily stored in a random access memory (RAM) but hasn't been programmed into a flash module;
• set an activation register to drive a search engine, wherein the search engine is arranged operably to:
• search for the entries in the sequential update queue to determine whether the second logical address range of any entry is entirely or partially overlapped with the first logical address range;
• and store a search result in a matching register and a resulting address register;
• check values of the matching register and the resulting address register to determine whether a whole or a portion of data of the first logical address range is temporarily stored in the RAM after a time period, wherein the value of the matching register is set by the search engine to indicate whether the second logical address range of any entry is entirely or partially overlapped with the first logical address range, and the value of the resulting address register is set by the search engine to indicate an entry address of the sequential update queue when the second logical address range of any entry is entirely or partially overlapped with the first logical address range;
• manipulate the whole or the portion of data of the first logical address range that is temporarily stored in the RAM when the whole or the portion of data of the first logical address range is temporarily stored in the RAM;
• read to-be-programmed data of a third logical address range in the first logical address range, which is overlapped with the second logical address range of the specific entry indicated by the resulting address register, from the RAM, and drive a flash interface to read data of a fourth logical address range in the first logical address range, which is not overlapped with the second logical address range of the specific entry indicated by the resulting address register, when the first logical address range is partially overlapped with the second logical address range of the specific entry indicated by the resulting address register;
• merge the to-be-programmed data of the third logical address range with the data of the fourth logical address range;
• and
• drive the host interface to reply to the host side with merged data.

An apparatus for executing host commands, comprising:

• a random access memory (RAM), arranged operably to allocate space for a sequential update queue and a data register, wherein the sequential update queue comprises a plurality of entries, each entry defines a second logical address range from a second start logical address to a second end logical address, and to-be-programmed data of each second logical address range is temporarily stored in the data buffer but hasn't been programmed into a flash module;
• a search engine, coupled to the RAM, comprising an activation register, arranged operably to:
• search for the entries in the sequential update queue to determine whether the second logical address range of any entry is entirely or partially overlapped with a first logical address range;
• and store a search result in a matching register and a resulting address register;
• and
• a processing unit, coupled to the RAM and the search engine, arranged operably to:
• set a first start register and a first end register to store the first logical address range from a first start logical address to a first end logical address for an execution of a host command;
• set the activation register to drive the search engine;
• check values of the matching register and the resulting address register to determine whether a whole or a portion of data of the first logical address range is temporarily stored in the data buffer after a time period, wherein the value of the matching register indicates whether the second logical address range of any entry is entirely or partially overlapped with the first logical address range, and the value of the resulting address register indicates an entry address of the sequential update queue when the second logical address range of any entry is entirely or partially overlapped with the first logical address range;
• manipulate the whole or the portion of data of the first logical address range that is temporarily stored in the data buffer when the whole or the portion of data of the first logical address range is temporarily stored in the data buffer;
• read to-be-programmed data of a third logical address range in the first logical address range, which is overlapped with the second logical address range of the specific entry indicated by the resulting address register, from the RAM, and drive a flash interface to read data of a fourth logical address range in the first logical address range, which is not overlapped with the second logical address range of the specific entry indicated by the resulting address register, when the first logical address range is partially overlapped with the second logical address range of the specific entry indicated by the resulting address register;
• merge the to-be-programmed data of the third logical address range with the data of the fourth logical address range;
• and drive the host interface to reply to the host side with merged data.