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US 12,530,148 B2Granted
Memory controller circuit and system for artificial neural network and method thereof
AssigneeDeepx Co., Ltd.
InventorLok Won Kim
Life of this patent
Estimating the term…
Abstract
According to an example of the present disclosure, a system is provided. A system may include a processor configured to output a memory control signal including an artificial neural network data locality, and a memory controller configured to receive the memory control signal from the processor and control a main memory in which data of an artificial neural network model corresponding to the artificial neural network data locality, is stored.
Claims20
A system comprising:
- a memory circuit configured to store an artificial neural network (ANN) model;
- a processor coupled to the memory circuit, the processor configured to:
- perform a sequence of read operations from the memory circuit and write operations to the memory circuit associated with the ANN model, and
- send data access requests corresponding to the sequence of the read operations and the write operations;
- and
- a memory controller circuit coupled to the memory circuit and the processor, the memory controller circuit configured to:
- receive the data access requests from the processor, and
- control access of the processor to the memory circuit based on the received data access requests.
5 more elements
A method, comprising:
- storing an artificial neural network (ANN) model in a memory circuit;
- performing, by a processor, a sequence of read operations from the memory circuit and write operations to the memory circuit associated with the ANN model;
- sending data access requests corresponding to the sequence of the read operations and the write operations from the processor to a memory controller circuit;
- and
- controlling access of the processor to the memory circuit by the memory controller circuit based on the data access requests.
2 more elements
A memory controller circuit, comprising:
- a cache memory circuit;
- and
- a logic circuit coupled to the cache memory circuit and configured to:
- determine a pattern of read operations and write operations associated with an artificial neural network (ANN) model stored in a memory circuit based on data access requests received from a processor by analyzing the data access requests,
- predict a memory address and an operation mode associated with a subsequent operation to be performed by the processor according to the determined pattern, and
- store data associated with the subsequent operation in the cache memory circuit before the processor sends a data request for the subsequent operation.
3 more elements
Dependencies are inferred from the claim text.