Methods and systems for communications between hardware components
AssigneeMicron Technology, Inc.
InventorsChristopher Baronne, Dean E. Walker, Bryan Hornung
Life of this patent
Estimating the term…
Abstract
Various examples are directed to systems and methods for executing a transaction between hardware compute elements of a computing system. A first hardware compute element may send a first write request to a second hardware compute element via a network structure. The first write request may comprise first source identifier data describing the first hardware compute element and first payload data describing a processing task requested by the first hardware compute element. The network structure may store first write request state data describing the first write request. Before the processing task is completed, the second hardware compute element may send a first write confirm message.
Claims20
A system for executing a transaction between hardware compute elements of a computing system, the system comprising:
- a first hardware compute element;
- a second hardware compute element;
- and
- a network structure, the system being configured to perform operations comprising:
- sending, by the first hardware compute element, a first write request to the second hardware compute element of the computing system via the network structure, the first write request comprising first source identifier data describing the first hardware compute element and first payload data describing a processing task requested by the first hardware compute element;
- providing, by the network structure, an address bus between the first hardware compute element and the second hardware compute element for providing the first source identifier data to the second hardware compute element;
- providing, by the network structure, a first write bus between the first hardware compute element and the second hardware compute element for providing the first payload data to the second hardware compute element;
- storing, by the network structure, first write request state data describing the first write request;
- before the processing task is completed, sending, by the second hardware compute element, a first write confirm message;
- and
- providing, by the network structure, a first write confirm bus between the second hardware compute element and the first hardware compute element, the first write confirm bus for providing the first write confirm message to the first hardware compute element.
A method of executing a transaction between hardware compute elements of a computing system, the method comprising:
- sending, by a first hardware compute element, a first write request to a second hardware compute element of the computing system via a network structure, the first write request comprising first source identifier data describing the first hardware compute element and first payload data describing a processing task requested by the first hardware compute element;
- providing, by the network structure, an address bus between the first hardware compute element and the second hardware compute element for providing the first source identifier data to the second hardware compute element;
- providing, by the network structure, a first write bus between the first hardware compute element and the second hardware compute element for providing the first payload data to the second hardware compute element;
- storing, by the network structure, first write request state data describing the first write request;
- before the processing task is completed, sending, by the second hardware compute element, a first write confirm message;
- and
- providing, by the network structure, a first write confirm bus between the second hardware compute element and the first hardware compute element, the first write confirm bus for providing the first write confirm message to the first hardware compute element.
A non-transitory computer-readable medium comprising instructions thereon that, when executed by a computing system comprising a first hardware compute element, a second hardware compute element, and a network structure, cause the computing system to perform operations comprising:
- sending, by the first hardware compute element, a first write request to the second hardware compute element of the computing system via the network structure, the first write request comprising first source identifier data describing the first hardware compute element and first payload data describing a processing task requested by the first hardware compute element;
- providing, by the network structure, an address bus between the first hardware compute element and the second hardware compute element for providing the first source identifier data to the second hardware compute element;
- providing, by the network structure, a first write bus between the first hardware compute element and the second hardware compute element for providing the first payload data to the second hardware compute element;
- storing, by the network structure, first write request state data describing the first write request;
- before the processing task is completed, sending, by the second hardware compute element, a first write confirm message;
- and
- providing, by the network structure, a first write confirm bus between the second hardware compute element and the first hardware compute element, the first write confirm bus for providing the first write confirm message to the first hardware compute element.
Dependencies are inferred from the claim text.