Integrated circuit layout method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPo-Zeng Kang, Wen-Shen Chou, Yung-Chow Peng
Life of this patent
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Abstract
A method of generating an IC layout diagram includes positioning a resistor unit cell in the IC layout diagram, a resistor of the resistor unit cell including a source/drain metal region, positioning a MOS unit cell in the IC layout diagram, overlapping the resistor unit cell with a first via region, overlapping the MOS unit cell with a second via region, overlapping the first and second via regions with a continuous conductive region, and storing the IC layout diagram in a storage device.
Claims20
A method of generating an integrated circuit (IC) layout diagram, the method comprising:
- positioning a resistor unit cell in a first cell row of the IC layout diagram, wherein a resistor of the resistor unit cell comprises a source/drain (S/D) metal region;
- positioning a metal oxide semiconductor (MOS) unit cell in a second cell row of the IC layout diagram adjacent to the first cell row of the IC layout diagram;
- overlapping the resistor unit cell with a first via region;
- overlapping the MOS unit cell with a second via region;
- overlapping the first and second via regions with a continuous conductive region;
- and
- storing the IC layout diagram in a storage device.
A method of generating an integrated circuit (IC) layout diagram, the method comprising:
- positioning a resistor unit cell in the IC layout diagram, wherein the resistor unit cell comprises a resistor comprising a first source/drain (S/D) metal region configured to define a first portion of a metal layer included in a completed IC device and overlapping a dielectric region;
- positioning a metal oxide semiconductor (MOS) unit cell in the IC layout diagram, wherein the MOS unit cell comprises a second S/D metal region configured to define a second portion of the metal layer included in the completed IC device and overlapping an active region;
- overlapping the first S/D metal region with a first via region;
- overlapping the second S/D metal region with a second via region;
- overlapping the first and second via regions with a continuous conductive region;
- and
- storing the IC layout diagram in a storage device.
A method of generating an integrated circuit (IC) layout diagram, the method comprising:
- positioning first and second resistor unit cells in a first row of the IC layout diagram, wherein each resistor unit cell comprises a resistor comprising a source/drain (S/D) metal region;
- positioning first and second metal oxide semiconductor (MOS) unit cells in a second row of the IC layout diagram;
- overlapping the resistor of the first resistor unit cell with a first via region;
- overlapping the first MOS unit cell with a second via region;
- overlapping the first and second via regions with a first continuous conductive region;
- overlapping the resistor of the second resistor unit cell with a third via region;
- overlapping the second MOS unit cell with a fourth via region;
- overlapping the third and fourth via regions with a second continuous conductive region;
- and
- storing the IC layout diagram in a storage device.
Dependencies are inferred from the claim text.