Semiconductor device with bootstrap diode

A method of manufacturing a semiconductor device comprising a diode, a low voltage region, a high voltage region, and a junction isolation region disposed between the low voltage region and the high voltage region,

• wherein the method of forming the diode comprises:
• forming a first N-type buried layer and a second N-type buried layer in a substrate;
• forming a first deep well region over the first N-type buried layer;
• forming a second deep well region over the second N-type buried layer;
• forming an N-type sink region in the first deep well region in direct contact with the first N-type buried layer;
• forming a first P-type body region in the first deep well region and surrounded by the N-type sink region;
• forming a second P-type body region in the second deep well region;
• forming a first insulating layer in direct contact with the second deep well region;
• forming a first polysilicon field plate over the first insulating layer;
• forming a P-type source region in the first P-type body region;
• forming an N-type drain region in the second deep well region and adjacent to the first polysilicon field plate;
• a first P-type buried layer disposed in the second deep well region between the first N-type buried layer and the second N-type buried layer, and spaced apart from the first insulating layer by a predetermined distance;
• forming an anode terminal electrically connected to the P-type source region;
• forming a cathode terminal electrically connected to the N-type drain region;
• forming a first terminal electrically connected to the second P-type body region;
• forming a first metal wire electrically connected to the anode terminal;
• and
• forming a second metal wire electrically connected to the cathode terminal and the first polysilicon field plate;
• forming a first upper metal wire electrically connected to the first terminal and the second P-type body region, the first upper metal wire extending to overlap with the first deep well region and the second deep well region;
• forming a second upper metal wire electrically connected to the second metal wire, the second upper metal wire extending to overlap with the first polysilicon field plate, and
• wherein the method of forming the junction isolation region comprises:
• forming a P-type isolation region configured to laterally surround the first and second N-type buried layers;
• forming a third P-type body region disposed adjacent to the P-type isolation region;
• forming a second polysilicon field plate disposed adjacent to the third P-type body region;
• forming a third metal wire electrically connected to the third P-type body region and the second polysilicon field plate;
• and
• forming a third upper metal wire electrically connected to the third metal wire, the third upper metal wire extending to overlap with the second polysilicon field plate.

A semiconductor device comprising a diode, a low voltage region, a high voltage region, a junction isolation region between the low voltage region and the high voltage region, and a laterally diffused metal-oxide semiconductor (LDMOS);

• wherein the diode comprises:
• a first N-type buried layer and a second N-type buried layer disposed in a substrate;
• a first deep well region of a first length disposed over the first N-type buried layer;
• a second deep well region of a second length greater than the first length disposed over the second N-type buried layer;
• an N-type sink region disposed in the first deep well region and in direct contact with the first N-type buried layer;
• a first P-type body region disposed in the first deep well region and surrounded by the N-type sink region;
• a second P-type body region disposed in the second deep well region;
• a first insulating layer in direct contact with the second deep well region;
• a first polysilicon field plate disposed on the first insulating layer;
• a P-type source region disposed in the first P-type body region;
• an N-type drain region disposed in the second deep well region and adjacent to the first polysilicon field plate;
• a first P-type buried layer disposed in the second deep well region between the first N-type buried layer and the second N-type buried layer, and spaced apart from the first insulating layer by a predetermined distance;
• an anode terminal electrically connected to the P-type source region;
• a cathode terminal electrically connected to the N-type drain region;
• a first terminal electrically connected to the second P-type body region;
• a first upper metal wire electrically connected to the first terminal and the second P-type body region, the first upper metal wire extending to overlap with the first deep well region and the second deep well region;
• a first metal wire electrically connected to the anode terminal;
• a second metal wire electrically connected to the cathode terminal and the first polysilicon field plate;
• and
• a second upper metal wire electrically connected to the second metal wire, the second upper metal wire extending to overlap with the first polysilicon field plate,
• wherein the junction isolation region comprises:
• a P-type isolation region configured to laterally surround the first and second N-type buried layers;
• a third P-type body region disposed adjacent to the P-type isolation region;
• a second polysilicon field plate disposed adjacent to the third P-type body region;
• and
• a third metal wire electrically connected to the third P-type body region and the second polysilicon field plate;
• and
• a third upper metal wire electrically connected to the third metal wire, the third upper metal wire extending to overlap with the second polysilicon field plate.