Fabrication of silicon carbide integrated power MOSFETs on a single substrate

A method of forming a Silicon Carbide (SiC) integrated circuit comprising:

• selecting a wafer for forming the SiC integrated circuit having a bulk layer with a first doping type and doping an epitaxial layer with a second doping type opposite of the first doping type to block current from flowing from the epitaxial layer to the bulk layer under normal voltage bias conditions and operation;
• forming a source region and a drain region for a first LDMOS device and a second LDMOS device in an epitaxial layer on the bulk layer;
• forming an isolation trench by etching between the first LDMOS device and the second LDMOS device, the isolation trench having sidewalls and a bottom;
• growing a thin layer of thermal oxide on the sidewalls and the bottom of the isolation trench;
• filling the isolation trench with an insulating trench fill material over the thermal oxide;
• forming in the epitaxial layer a body region of first LDMOS device and a body region of the second LDMOS device, wherein the body region of the first LDMOS and the body region of the second LDMOS device are electrically isolated from each other by the insolation trench, allowing the first LDMOS device and the second LDMOS device to exist on a same die and have different voltage bias levels maintained at body nodes of the first LDMOS and the second LDMOS device;
• completing the first LDMOS device and the second LDMOS device including forming gate structures and metallization layers;
• and
• packaging the first LDMOS device and second LDMOS device formed together in the epitaxial layer on the bulk layer of the SiC integrated circuit as a single semiconductor die in a single package.