Method of manufacturing semiconductor devices having metal gate structure and semiconductor devices

A method of manufacturing a semiconductor device, the method comprising:

• forming a dummy gate structure over a substrate, the dummy gate structure including a dummy gate dielectric layer and a dummy gate electrode layer;
• forming sidewall spacers including one or more layers of insulating materials on sidewalls of the dummy gate structure;
• forming a silicon based liner over the sidewall spacers, wherein a thickness of the silicon based liner is greater at a base of the dummy gate structure than a thickness of the silicon based liner at a top of the dummy gate structure;
• forming a first insulating layer over the silicon based liner;
• thermally treating the silicon based liner and the first insulating layer, and thereby reduce a volume of the first insulating layer and increase a volume of the silicon based liner;
• removing the dummy gate structure to form a gate space in the first insulating layer, wherein a gate critical dimension (CD) at or adjacent a top portion of the gate space is larger than a gate CD at or adjacent a bottom portion of the gate space;
• and
• filling the gate space with a high-k dielectric layer and a first conductive layer,
• wherein the dummy gate electrode layer has a width Wg and the gate space has a width Ws at or adjacent a top of the dummy gate structure, and the width Ws is smaller than Wg.

A semiconductor device comprising:

• a channel region;
• a gate dielectric layer disposed over the channel region;
• a gate electrode layer disposed over the gate dielectric layer;
• gate sidewall spacers between which the gate electrode layer and gate dielectric layer are disposed;
• and
• a source and a drain, wherein
• in a cross section along a source-to-drain direction, a distance between the gate sidewall spacers decreases along a vertical direction from a top of the gate sidewall spacers to a middle of the gate sidewall spacers and increases along the vertical direction from the middle of the gate sidewall spacers to a bottom of the gate sidewall spacers, such that a gate space between adjacent gate sidewall spacers is arc-shaped.