Bidirectional thyristor

A bidirectional thyristor, comprising:

• a first first-conductivity-type semiconductor layer;
• a first second-conductivity-type semiconductor layer disposed on a rear surface side of the first first-conductivity-type semiconductor layer;
• a second first-conductivity-type semiconductor layer disposed on a rear surface side of the first second-conductivity-type semiconductor layer;
• a second second-conductivity-type semiconductor layer disposed on a rear surface side of the second first-conductivity-type semiconductor layer;
• a third second-conductivity-type semiconductor layer disposed on a front surface side of the first first-conductivity-type semiconductor layer;
• a plurality of carrier emitting portions disposed in the third second-conductivity-type semiconductor layer;
• a fourth second-conductivity-type semiconductor layer disposed on the front surface side of the first first-conductivity-type semiconductor layer;
• a first electrode that contacts the third second-conductivity-type semiconductor layer, the plurality of carrier emitting portions, and the first first-conductivity-type semiconductor layer;
• a second electrode that contacts the second second-conductivity-type semiconductor layer and the second first-conductivity-type semiconductor layer;
• a gate electrode that contacts the fourth second-conductivity-type semiconductor layer and the first first-conductivity-type semiconductor layer;
• and
• a passivation film disposed on a boundary between the first first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer and a boundary between the first second-conductivity-type semiconductor layer and the second first-conductivity-type semiconductor layer on the front surface side of the first first-conductivity-type semiconductor layer, wherein
• each of the plurality of carrier emitting portions is configured such that an opening is formed in the third second-conductivity-type semiconductor layer and the first first-conductivity-type semiconductor layer is located in the opening,
• in plan view, the plurality of carrier emitting portions are disposed between a position away from the gate electrode by a predetermined distance and an outer edge of the first electrode,
• two or more of the plurality of carrier emitting portions are disposed in contact with the outer edge of the first electrode which contacts the passivation film, and
• in plan view, an area of a triangle formed by adjacent carrier emitting portions located at the outer edge of the first electrode and a carrier emitting portion located at a shortest distance from a straight line connecting the adjacent carrier emitting portion is smaller than an area of a quadrangle formed by carrier emitting portions that are not located at the outer edge of the first electrode.