Methods of forming a device, and related devices, memory devices, and electronic systems

A device, comprising:

• a first barrier structure substantially impermeable to hydrogen;
• conductive line structures overlying the first barrier structure and laterally extending in a first direction, the conductive line structures comprising one or more of Ru, Mo, and TiN;
• channel pillars overlying the conductive line structures and each comprising one or more of ZnxSnyO, InxZnyO, ZnxO, InxGayZnzO, InxGaySizOa, InxWyO, InxO, SnxO, TixO, ZnxONz, MgxZnyO, ZrxInyZnzO, HfxInyZnzO, SnxInyZnzO, AlxSnyInzZnaO, SixInyZnzO, AlxZnySnzO, GaxZnySnzO, and ZrxZnySnzO;
• dielectric liner structures substantially laterally surrounding sidewalls of the channel pillars;
• gate electrodes laterally adjacent outer sidewalls of the dielectric liner structures and laterally extending in a second direction substantially perpendicular to the first direction;
• conductive contacts overlying the channel pillars;
• and
• a second barrier structure substantially impermeable to hydrogen overlying and laterally extending across upper surfaces of the dielectric liner structures and the gate electrodes,
• the second barrier structure in direct physical contact with the dielectric liner structures, and
• the first barrier structure and the second barrier structure each individually comprising one or more of AlOx, AlOxNy, AlSixNy, and AlSixOyNz.

A memory device, comprising:

• word lines;
• digit lines;
• a barrier structure underlying the digit lines and comprising one or more of AlOx, AlOxNy, AlSixNy, and AlSixOyNz;
• lines;
• memory cells overlying the barrier structure and electrically coupled to the word lines and the digit lines, each memory cell comprising:
• a vertical transistor electrically coupled to at least one of the word lines, the vertical transistor comprising:
• a channel pillar over one of the digit lines and laterally neighboring the at least one of the word lines, the channel pillar comprising at least one semiconductor material having a larger bandgap than polycrystalline silicon;
• and
• a dielectric liner structure between the channel pillar and the at least one of the word lines;
• and
• a capacitor electrically coupled to the vertical transistor;
• an additional barrier structure overlying the at least one of the word lines and the dielectric liner structure of each of the memory cells and comprising one or more of AlOx, AlOxNy, AlSixNy, and AlSixOyNz, a lower portion of the capacitor of each of the memory cells vertically extending entirely through the additional barrier structure;
• and
• another barrier structure overlying the memory cells and comprising one or more of AlOx, AlOxNy, AlSixNy, and AlSixOyNz.

An electronic system, comprising:

• an input device;
• an output device;
• a processor device operably coupled to the input device and the output device;
• and
• a device operably coupled to the processor device and comprising:
• a first barrier structure comprising one or more of AlOx, AlOxNy, AlSixNy, and AlSixOyNz;
• a vertical transistor overlying the first barrier structure and comprising:
• a channel structure comprising at least one semiconductor material having a larger bandgap than polycrystalline silicon;
• a gate dielectric material laterally surrounding the channel structure;
• and
• a gate electrode laterally adjacent the gate dielectric material;
• and
• a second barrier structure overlying the gate dielectric material and the gate electrode of the vertical transistor, the second barrier structure comprising one or more of AlOx, AlOxNy, AlSixNy, and AlSixOyNz.