Three-dimensional memory devices
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsKun Zhang, Wenxi Zhou, Zhiliang Xia, Zongliang Huo
Life of this patent
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Abstract
A three-dimensional (3D) memory device is disclosed. The 3D memory device includes a memory stack, a semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack, and a source contact above the memory stack and in contact with the semiconductor layer. A semiconductor plug, in contact with the semiconductor layer, surrounds an end of one of the channel structures. The source contact is electrically connected with the one of the channel structures. At least a portion of the source contact is buried within the semiconductor layer.
Claims20
A three-dimensional (3D) memory device, comprising:
- a memory stack comprising interleaved conductive layers and dielectric layers;
- a semiconductor layer above the memory stack;
- a plurality of channel structures each extending vertically through the memory stack, a semiconductor plug, in contact with the semiconductor layer, surrounding an end of one of the channel structures;
- a source contact above the memory stack and in contact with the semiconductor layer, wherein the source contact is electrically connected with the one of the channel structures, at least a portion of the source contact being buried within the semiconductor layer;
- and
- an interconnect layer disposed at a side of the memory stack where the source contact is located.
A three-dimensional (3D) memory device, comprising:
- a peripheral circuit;
- a memory stack arranged above the peripheral circuit and comprising interleaved conductive layers and dielectric layers;
- a semiconductor layer above the memory stack;
- a plurality of channel structures each extending vertically through the memory stack, a semiconductor plug, in contact with the semiconductor layer, surrounding an end of one of the channel structures;
- and
- a source contact above the memory stack and in contact with the semiconductor layer,
- wherein:
- the peripheral circuit is electrically connected with the one of the channel structures;
- and
- the peripheral circuit and an interconnect layer disposed on the semiconductor layer are arranged at opposite sides of the memory stack.
A three-dimensional (3D) memory device, comprising:
- a first semiconductor structure comprising a peripheral circuit;
- a second semiconductor structure comprising:
- a memory stack comprising interleaved conductive layers and dielectric layers;
- a semiconductor layer above the memory stack;
- a plurality of channel structures each extending vertically through the memory stack;
- and
- a source contact arranged above the memory stack, a portion of the source contact being buried within the semiconductor layer, and another portion of the source contact being disposed outside the semiconductor layer toward a side opposite the memory stack;
- and
- a bonding interface between the first semiconductor structure and the second semiconductor structure,
- wherein:
- the one of the channel structures is electrically connected with the peripheral circuit through at least the semiconductor layer, the source contact, and the bonding interface;
- and
- the peripheral circuit and the source contact are arranged at opposite sides of the memory stack.
Dependencies are inferred from the claim text.