Floor lamp control circuit

A floor lamp control circuit, comprising a central processing unit (CPU) (1);

• a 12-36V isolation adapter (2);
• a DC-DC step-down circuit (3);
• and an H-bridge control LED brightness and color temperature circuit (4);
• wherein the input end of the 12-36V isolation adapter (2) is connected to the mains supply, the output end of the 12-36V isolation adapter (2) is connected to the input end of the DC-DC step-down circuit (3), the output end of the DC-DC step-down circuit (3) is connected to the CPU (1);
• the two PWM control ports of the CPU (1) are connected to the two PWM ports of the H-bridge control LED brightness and color temperature circuit (4) respectively;
• and the conduction of the H-bridge control LED brightness and color temperature circuit (4) is controlled through two PWM control ports;
• the output end of the LED brightness and color temperature circuit (4) is connected in parallel with a plurality of LED lamp arrays (5);
• the H-bridge control LED brightness and color temperature circuit (4) comprises a +24V VCC, a first NPN transistor Q1, a second PNP transistor Q2, a third NPN transistor Q3, a fourth PNP transistor Q4, a first P-channel field effect transistor P1, a second N-channel field effect transistor P2, a third P-channel field effect transistor P3, a fourth N-channel field effect transistor P4, a fifth N-channel field effect transistor P5 and a sixth N-channel field effect transistor P6;
• the S-pin of the sixth N-channel field effect transistor P6 is connected to the ground terminal GND;
• one G-pin end of the sixth N-channel field effect transistor P6 is connected to a third resistor R3, and the other end of the third resistor R3 serves as a PWM interface II and is connected to a PWM control port of the CPU (1);
• the D-pin of the sixth N-channel field effect transistor P6 is connected to the base of the second PNP transistor Q2 through a second resistor R2, and the collector of the second PNP transistor Q2 is connected to the ground terminal GND through a fourth resistor R4;
• the emitter of the second PNP transistor Q2 is connected to that of the first NPN transistor Q1, and the base of the first NPN transistor Q1 is connected to that of the second PNP transistor Q2;
• the collector of the first NPN transistor Q1 is connected to the +24V VCC, and the +24V VCC is connected to the G-pin of the first P-channel field effect transistor P1 through a fifteenth resistor R15;
• the G-pin of the first P-channel field effect transistor P1 is further connected to the emitter of the second PNP transistor Q2 through a sixteenth resistor R16;
• the S-pin of the first P-channel field effect transistor P1 is connected to the +24V VCC, the D-pin of the first P-channel field effect transistor P1 is connected to that of the second N-channel field effect transistor P2 and serves as a solder pad interface A;
• the S-pin of the second N-channel field effect transistor P2 is connected to the ground terminal GND, the G-pin of the second N-channel field effect transistor P2 is connected to one end of the a fifth resistor R5, and the other end of the fifth resistor R5 serves as a PWM interface I and is connected to another PWM control port of the CPU (1);
• the S-pin of the fifth N-channel field effect transistor P5 is connected to the ground terminal GND, one G-pin end of the fifth N-channel field effect transistor P5 is connected to a fourteenth resistor R14, and the other end of the fourteenth resistor R14 serves as a PWM interface I and is connected to a PWM control port of the CPU (1);
• the D-pin of the fifth N-channel field effect transistor P5 is connected to the base of the fourth PNP transistor Q4 through a twelfth resistor R12, the collector of the fourth PNP transistor Q4 is connected to the ground terminal GND through a seventeenth resistor R17, and the emitter of the fourth PNP transistor Q4 is connected to that of the third NPN transistor Q3;
• the base of the third NPN transistor Q3 is connected to that of the fourth PNP transistor Q4, the collector of the third NPN transistor Q3 is connected to the +24V VCC, and the +24V VCC is connected to the G-pin of the third P-channel field effect transistor P3 through a tenth resistor R10;
• the G-pin of the third P-channel field effect transistor P3 is further connected to the emitter of the fourth PNP transistor Q4 through an eleventh resistor R11, the S-pin of the third P-channel field effect transistor P3 is connected to the +24V VCC, the D-pin of the third P-channel field effect transistor P3 is connected to that of the fourth N-channel field effect transistor P4 and serves as a solder pad interface B;
• the S-pin of the fourth N-channel field effect transistor P4 is connected to the ground terminal GND;
• the G-pin of the fourth N-channel field effect transistor P4 is connected to one end of an eighth resistor R8;
• and the other end of the eighth resistor R8 serves as a PWM interface II and is connected to another PWM control port of the CPU (1).