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US 12,525,990 B2Granted
Commands for testing error correction in a memory device
AssigneeMicron Technology, Inc.
InventorFrancesco Lupo
Life of this patent
Estimating the term…
Abstract
Systems, methods, and apparatus related to error correction in memory devices. In one approach, a memory device uses dedicated op-codes to generate, during programming operations, a pattern including known requested data errors. During reading operations on the memory device, the calibrated errors will be detected by the ECC engine of the memory device as read errors. This permits a host device to observe, in a controlled environment, how the ECC engine behaves and performs in a final manufactured memory product.
Claims25
A system comprising:
- memory configured to store user data for a host device;
- an error correction code (ECC) engine configured to generate error correction code (ECC) data for the stored user data, wherein the ECC data provides a capability for correcting at least one error in the user data;
- and
- a controller configured to:
- receive, from the host device, a command requesting at least one error to inject into stored data, wherein the command is a test command;
- in response to receiving the command, generate first data and first ECC data that correspond to the requested error, wherein the first ECC data is generated using the ECC engine;
- store the first data and first ECC data in the memory;
- read the first data and the first ECC data from the memory;
- perform, using the ECC engine, error correction for the first data read from the memory, the error correction using the first ECC data to detect the requested error;
- signal the host device to indicate detection of the requested error,
- wherein the controller is further configured to operate in a standard mode or a test mode;
- receiving a read or write command associated with user data from the host device causes the controller to operate in the standard mode;
- and
- receiving the test command causes the controller to operate in the test mode;
- wherein the status register is configured for access by the host device to determine:
- when in the standard mode, a status of a read or write operation for user data received from the host device;
- or
- when in the test mode, a status of at least one of storing the first data, reading the first data, or performing error correction for the first data.
15 more elements
A system comprising:
- memory;
- an error correction code (ECC) engine;
- and
- a controller configured to:
- receive, from a host device, a command requesting at least one error to inject into data programmed in the memory;
- in response to receiving the command, store and read first data, wherein:
- storing the first data comprises generating, based on the requested error and using the ECC engine, the first data and first ECC data, and programming the first data and first ECC data in the memory;
- and
- reading the first data comprises reading the first data and the first ECC data from the memory, and performing, using the ECC engine and the first ECC data, error correction for the first data read from the memory;
- and
- signal the host device regarding the error correction,
- wherein second data is read from the memory;
- error correction is performed by the ECC engine for the second data;
- and
- a behavior of the error correction for the first data is compared to a behavior of the error correction for the second data.
12 more elements
A method comprising:
- receiving, from a host device, a command requesting at least one error, wherein the command is a test command;
- in response to receiving the command, generating first data and first ECC data that correspond to the requested error;
- storing the first data and first ECC data in memory;
- reading the first data and the first ECC data from the memory;
- performing error correction for the first data read from the memory, the error correction using the first ECC data to detect the requested error;
- signaling the host device regarding the error correction;
- and
- operating in a standard mode or a test mode;
- wherein second data is read from the memory;
- error correction is performed by the ECC engine for the second data;
- and
- a behavior of the error correction for the first data is compared to a behavior of the error correction for the second data.
9 more elements
Dependencies are inferred from the claim text.