US 12,525,923 B2 · Equalizer circuit in an envelope tracking integrated circuit

Abstract

An equalizer circuit in an envelope tracking (ET) integrated circuit (ETIC) is disclosed. The ETIC (26) is configured to generate an ET voltage based on a target voltage (VTGT) for amplifying a radio frequency (RF) signal(s). Since the ETIC has inherent impedance and group delay that can cause distortion in the ET voltage, an equalizer circuit (24) is provided in the ETIC to equalize the target voltage prior to generating the ET voltage. Specifically, the equalizer circuit generates an equalized target voltage to offset the inherent impedance and a modified target voltage to mitigate the group delay. Accordingly, the equalizer circuit can output a processed target voltage, which can include the equalized target voltage and/or the modified target voltage, for generating the ET voltage. As a result, it is possible to reduce distortion resulted from the inherent impedance and group delay, especially when the RF signal(s) is modulated in a wide modulation bandwidth.

Claims18

Dependent claims

An equalizer circuit comprising:

a voltage input that receives a target voltage;
an impedance equalizer circuit configured to equalize the target voltage based on a predefined transfer function to generate an equalized target voltage;
a target voltage processing circuit configured to modify the target voltage to generate a modified target voltage having a reduced dynamic range lower than the target voltage;
an output circuit (38) configured to:
receive the equalized target voltage and the modified target voltage and output a processed target voltage comprising both the equalized target voltage and the modified target voltage when the target voltage is associated with a higher modulation bandwidth;
and
receive only the equalized target voltage and generate the processed target voltage comprising only the equalized target voltage when the target voltage is associated with a lower modulation bandwidth lower than the higher modulation bandwidth;
and
a voltage output coupled to the output circuit and outputting the processed target voltage.

6 more elements

An envelope tracking (ET) integrated circuit (ETIC) comprising:

an equalizer circuit comprising:
a voltage input that receives a target voltage;
an impedance equalizer circuit configured to equalize the target voltage based on a predefined transfer function to generate an equalized target voltage;
a target voltage processing circuit configured to modify the target voltage to generate a modified target voltage having a reduced dynamic range lower than the target voltage;
an output circuit configured to:
receive the equalized target voltage and the modified target voltage and output a processed target voltage comprising both the equalized target voltage and the modified target voltage when the target voltage is associated with a higher modulation bandwidth;
and
receive only the equalized target voltage and generate the processed target voltage comprising only the equalized target voltage when the target voltage is associated with a lower modulation bandwidth lower than the higher modulation bandwidth;
and
a voltage output coupled to the output circuit and outputs the processed target voltage;
and
an ET voltage circuit coupled to the voltage output and configured to generate an ET voltage based on the processed target voltage.

9 more elements

Dependencies are inferred from the claim text.

Equalizer circuit in an envelope tracking integrated circuit

Life of this patent

Equalizer circuit in an envelope tracking integrated circuit

Life of this patent

Abstract

Claims18