Input matching network with harmonic trap for frequency multiplier
AssigneeAnalog Devices, Inc.
InventorHsin-Chang Lin
Life of this patent
Estimating the term…
Abstract
Aspects of this disclosure relate to a frequency multiplier with a transmission line in an input matching network. The frequency multiplier can multiply a frequency of a radio frequency input signal. The transmission line can provide a second harmonic trap. The transmission line can be electrically connected between input terminals of a pair of balanced transistors of the frequency multiplier.
Claims20
A frequency multiplication circuit for multiplying frequency of a radio frequency signal, the frequency multiplication circuit comprising:
- a frequency multiplier configured to multiply a frequency of a radio frequency input signal and to generate a radio frequency output signal, the frequency multiplier comprising a pair of balanced transistors;
- and
- an input matching network coupled to the frequency multiplier, the input matching network comprising a transmission line electrically connected between an input terminal of a first transistor of the pair of balanced transistors and an input terminal of a second transistor of the pair of balanced transistors, the transmission line configured to provide a frequency trap for an even harmonic of the radio frequency input signal and to present a shunt inductance to ground at a frequency of the radio frequency input signal.
A frequency multiplication circuit for multiplying frequency of a radio frequency signal, the frequency multiplication circuit comprising:
- a frequency multiplier comprising a pair of balanced transistors, the frequency multiplier configured to receive a radio frequency input signal and generate a radio frequency output signal having a frequency that is two times a frequency of the radio frequency output signal;
- and
- an input matching network comprising a transmission line electrically connected between an input terminal of a first transistor of the pair of balanced transistors and an input terminal of a second transistor of the pair of balanced transistors, the transmission line having a length of λ/4 where λ is a wavelength of the radio frequency input signal, and the transmission line configured to present a short circuit impedance at an even harmonic of the radio frequency input signal and to present a shunt inductor at the frequency of the radio frequency input signal.
An antenna on a chip with frequency multiplication circuitry, the antenna on the chip comprising:
- an oscillator;
- a frequency multiplier coupled to an output of the oscillator, the frequency multiplier comprising a pair of balanced transistors, the frequency multiplier configured to receive a radio frequency input signal and generate a radio frequency output signal having a frequency that is two times a frequency of the radio frequency input signal;
- an input matching network comprising a transmission line configured to provide a frequency trap for a second harmonic of the radio frequency input signal and to present a shunt inductance to ground at a frequency of the radio frequency input signal, the transmission line electrically connected between an input terminal of a first transistor of the pair of balanced transistors and an input terminal of a second transistor of the pair of balanced transistors;
- and
- an antenna coupled to the frequency multiplier, wherein the oscillator, the frequency multiplier, the input matching network, and the antenna are embodied on a single chip.
Dependencies are inferred from the claim text.