Semiconductor devices and methods of manufacturing the same

A semiconductor device comprising:

• a standard cell array including a first plurality of standard cells and a second plurality of standard cells;
• a plurality of power supply lines configured to provide a power supply voltage and extending in a first direction;
• a capacitor structure including electrode structures included in each of a plurality of dielectric layers formed on the standard cell array, and the capacitor structure further having vias connecting the electrode structures;
• and
• contacts electrically connecting the capacitor structure and the standard cell array to each other, wherein:
• each of the first plurality of standard cells includes a first transistor connected to a first power supply line of the plurality of power supply lines, and a second transistor connected to a second power supply line of the plurality of power supply lines, and each of the first plurality of standard cells configured to provide a unit capacitor circuit having a capacitance that is based on a connection structure of (i) active regions of the first and second transistors thereof and the first and second power supply lines and (ii) gates of the first and second transistors thereof and the first and second power supply lines,
• for each of the first plurality of standard cells, the first power supply line is configured to provide a first power supply voltage and is connected to a first active region of the first transistor thereof, the second power supply line is configured to provide a second power supply voltage that is connected to a first active region of the second transistor thereof,
• the connection structure of the gates of the first and second transistors and the first and second power supply lines of a first set of the first plurality of standard cells is different from the connection structure of the gates of the first and second transistors and the first and second power supply lines of a second set of the first plurality of standard cells,
• a first voltage level of the gates of the first transistors of the first set of the first plurality of standard cell and a second voltage level of the gates of the first transistors of the second set of the first plurality of standard cells are different each other,
• the second plurality of standard cells has a different connection structure from the first plurality of standard cells and includes a fourth standard cell,
• a third transistor of the fourth standard cell is connected to a third power supply line of the plurality of power supply lines, and a fourth transistor of the fourth standard cell is connected to the third power supply line and includes impurities having a conductivity type that is different from a conductivity type of the third transistor of the fourth standard cell, and
• in the fourth standard cell, the third power supply line is configured to provide the first power supply voltage and is connected to the active regions and gates of the third and fourth transistors.