US 12,525,452 B2Granted

Semiconductor structure and method for fabricating same

AssigneeChangxin Memory Technologies, Inc.

InventorsGongyi Wu, Xiaofei Wu, Yachao Xu

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Abstract

Embodiments discloses a semiconductor structure and a fabricating method. The method includes: forming a contact hole on a substrate; forming a first doped layer on a surface of the contact hole, and annealing the first doped layer; forming at least one second doped layer on the first doped layer, and annealing each of the at least one second doped layer; and forming a third doped layer on the at least one second doped layer to fill up the contact hole. A thickness of the at least one second doped layer is greater than a thickness of the third doped layer, and the thickness of the third doped layer is greater than the thickness of the first doped layer. Annealing not only can repair lattice mismatch and lattice defect in the first doped layer/second doped layer, but also can improve surface roughness of the first doped layer/second doped layer.

Claims10

Dependent claims

A method for fabricating a semiconductor structure, comprising:

forming a contact hole on a substrate;
forming a first doped layer on a surface of the contact hole, and annealing and etching the first doped layer, such that a thickness of the first doped layer positioned at an upper part of the contact hole is less than a thickness of the first doped layer positioned at a lower part of the contact hole after etching;
forming at least one second doped layer on a surface of the first doped layer, and annealing and etching the at least one second doped layer after each of the at least one second doped layer is formed, such that a thickness of the at least one second doped layer positioned at the upper part of the contact hole is less than a thickness of the at least one second doped layer positioned at the lower part of the contact hole after etching;
and
forming a third doped layer on the at least one second doped layer to fill up the contact hole;
wherein the thickness of the at least one second doped layer is greater than a thickness of the third doped layer, and the thickness of the third doped layer is greater than the thickness of the first doped layer.

3 more elements

A semiconductor structure, comprising:

a substrate comprising a contact hole;
a first doped layer provided on a surface of the contact hole, wherein a thickness of the first doped layer positioned at an upper part of the contact hole is less than a thickness of the first doped layer positioned at a lower part of the contact hole;
at least one second doped layer provided on a surface of the first doped layer, wherein a thickness of the at least one second doped layer positioned at the upper part of the contact hole is less than a thickness of the at least one second doped layer positioned at the lower part of the contact hole;
and
a third doped layer provided on a surface of the at least one second doped layer and filling up the contact hole, wherein a thickness of the third doped layer positioned at the upper part of the contact hole is greater than a thickness of the third doped layer positioned at the lower part of the contact hole;
wherein the thickness of the at least one second doped layer is greater than a thickness of the third doped layer, and the thickness of the third doped layer is greater than the thickness of the first doped layer.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/971,632Filed 23 Oct 2022
Priority: CN 202111242965.825 Oct 2021
Published: US 2023/0125245 A127 Apr 2023
Granted: 13 Jan 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10P 32/12
Diffusion of dopants within, into or out of semiconductor bodies or layers: between a solid phase and a gaseous phase
H10B 12/01
Dynamic random access memory [DRAM] devices: manufacture or treatment
H10P 32/171
Characterised by the semiconductor material: being group IV material
H10P 50/266
By chemical means: by vapour etching only