Functional safety mechanisms for input/output (IO) cells

A system comprising:

• a memory storing instructions;
• and
• a processor, coupled with the memory and to execute the instructions, the instructions, when executed, to cause the processor to:
• receive data to be programmed to one or more memory cells of the memory;
• provide the received data to a receiving buffer of an input/output (IO) cell;
• transmit the received data from the receiving buffer to a latching component of the IO cell;
• transmit the data from the latching component through a transmission buffer of the IO cell;
• obtain the data from the transmission buffer;
• and
• responsive to detecting a first mismatch between the received data at the receiving buffer and the data obtained from the transmission buffer, determine that a fault has occurred at one or more of the receiving buffer or the transmission buffer, wherein to determine that the fault has occurred at the one or more of the receiving buffer or the transmission buffer the processor is to:
• obtain testing data via a dedicated testing pin of a multiplexor component coupled to the transmission buffer;
• provide the testing data to the transmission buffer;
• obtain the testing data from the transmission buffer;
• and
• responsive to detecting a second mismatch between the testing data obtained via the dedicated testing pin and the testing data obtained from the transmission buffer, determine that the fault has occurred at the transmission buffer.

A method comprising:

• identifying a first data stream of a transmission buffer through an input/output (IO) cell of a device;
• identifying a second data stream of a receiving buffer through the IO cell;
• providing the first data stream and the second data stream as an input to an exclusive- or (XOR) logic gate of the IO cell;
• determining, based on an output of the XOR logic gate, whether a first mismatch is detected between the first data stream and the second data stream, wherein the first mismatch indicates a fault at one or more of the transmission buffer or the receiving buffer;
• responsive to determining that the first mismatch is detected between the first data and the second data, transmitting, to a processor of the device, a signal indicating the fault at the one or more of the transmission buffer or the receiving buffer;
• obtaining testing data via a dedicated testing pin of a multiplexor component coupled to the transmission buffer;
• providing the testing data to the receiving buffer;
• obtaining the testing data from the receiving buffer;
• and
• responsive to detecting a second mismatch between the testing data obtained via the dedicated testing pin of the multiplexor component and the testing data obtained from the receiving buffer, determining that the fault has occurred at the receiving buffer.