Enhanced Harvard architecture reduced instruction set computer (RISC) with debug mode access of instruction memory within a unified memory space

A Harvard-architecture computer with a debug mode comprising:

• an instruction memory for storing program code;
• a data memory for storing program data;
• a first switch;
• an instruction bus between the first switch and the instruction memory;
• a data bus to the data memory;
• a processor Integrated Circuit (IC) which comprises:
• a debug module having an external interface to an external debugger;
• a debug mode register in the debug module, the debug mode register having a debug mode bit that indicates a debug mode;
• a debug address register, in the debug module, for storing a debug address received from the external interface;
• a debug data register, in the debug module, for receiving write data from the external interface, and for storing read data to be sent over the external interface;
• an execution core for executing instructions;
• a load/store unit in the execution core for generating a data address;
• a register bank, accessible by the execution core, for storing data;
• a second switch that connects the load/store unit to the data bus when the debug mode bit is not active, allowing the load/store unit to send the data address through the second switch to the data bus to the data memory, the second switch also sending write data from the register bank to the data bus for writing into the data memory for store instructions, the second switch transferring data read from the data memory and sent over the data bus to the register bank for load instructions;
• the second switch disconnecting the load/store unit and connecting the debug module to the data bus when the debug mode bit is active;
• an instruction pointer that generates an instruction address that is sent to the first switch;
• an instruction buffer that receives an instruction read from the instruction memory and sent over the data bus through the first switch;
• and
• an instruction decoder that decodes the instruction in the instruction buffer to control execution by the execution core;
• wherein the first switch sends the instruction address from the instruction pointer over the instruction bus to the instruction memory, the instruction memory reading the instruction at the instruction address and sending the instruction over the instruction bus and through the first switch to the instruction buffer, when the debug mode bit is not active;
• wherein when the debug mode bit is active, the first switch disconnects the instruction pointer and the instruction buffer from the instruction bus, the first switch connecting the instruction bus to the data bus when the debug mode bit is active;
• wherein when the debug mode bit is active, the debug module accesses instructions in the instruction memory by sending the debug address through the second switch, the data bus, the first switch, and the instruction bus to the instruction memory;
• wherein when the debug mode bit is active, the debug module accesses data in the data memory by sending the debug address through the second switch and the data bus, to the data memory,
• whereby the debug module is able to access instructions through the first switch and the second switch when the debug mode bit is activated.

A debugable Harvard architecture computer system comprising:

• an instruction memory for storing instructions;
• a data memory for storing data;
• an instruction bus connected to the instruction memory, the instruction bus carrying an instruction address to the instruction memory, the instruction bus carrying an instruction read from the instruction memory;
• a data bus connected to the data memory, the data bus carrying a data address to the data memory and carrying data read from the data memory;
• a processing core that receives the instruction and performs operations specified by the instruction, including a load operation that generates the data address and receives data that was previously stored in the data memory at the data address, the processing core also generating the instruction address;
• a debug module having an external interface to an external debugger;
• a debug mode register having a debug mode indicator that is active when the external debugger is debugging the debugable Harvard architecture computer system and that is inactive when the processing core is executing instructions;
• a first switch between the processing core and the instruction bus, the first switch sending the instruction address from the processing core to the instruction bus to the instruction memory and returning the instruction read from the instruction memory and sent over the instruction bus to the processing core when the debug mode indicator is inactive;
• when the debug mode indicator is active, the first switch isolating the processing core from the instruction bus, the first switch connecting the data bus to the instruction bus to allow access of the instruction memory through the data bus;
• and
• a second switch connecting the processing core to the data bus when the debug mode indicator is inactive, the processing core accessing the data memory by sending the data address through the second switch to the data bus, the processing core receiving data read from the data memory over the data bus and through the second switch;
• when the debug mode indicator is active, the second switch isolating the processing core from the data bus, the second switch connecting the data bus to the debug module to allow the debug module to access the data memory through the data bus, and access the instruction memory through the data bus connected to the instruction bus by the first switch,
• wherein the debug module reads both the data memory and the instruction memory during a debug mode when the processing core is not executing instructions.