Bus configuration system and method thereof
AssigneeRichtek Technology Corporation
InventorsChing-Yi Chen, Hsing-Shen Huang, Bo-Jyun Huang
Life of this patent
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Abstract
A bus configuration system includes a plurality of driver integrated circuits (ICs) coupled sequentially on a daisy chain, and a bus controller coupled to the plurality of driver ICs. Each driver IC includes a plurality of ports. The bus controller is used to generate a port definition code for configuring each port of the each driver IC. The bus controller includes a clock output port used to output a clock signal and a data output port used to output a data signal. When a port of the plurality of ports detects the clock signal, the port is configured as a clock input port.
Claims20
A bus configuration system, comprising:
- a plurality of driver integrated circuits (ICs) coupled sequentially on a daisy chain, each driver IC comprising a plurality of ports;
- and
- a bus controller coupled to the plurality of driver ICs, and comprising a clock output port and a data output port;
- wherein when a port of the plurality of ports detects the clock signal, the port is configured as a clock input port based on the detection of a clock signal;
- in response to the clock input port being configured, the bus controller generates and transmits a port definition code based on the clock input port, the port definition code configuring the plurality of ports of each driver IC.
A bus configuration system, comprising:
- a plurality of driver integrated circuits (ICs) coupled sequentially on a daisy chain, each driver IC comprising:
- a first port, a second port, a third port and a fourth port;
- and
- a port mapping rule;
- and
- a bus controller coupled to the plurality of driver ICs, comprising:
- a clock output port and a data output port;
- wherein when a clock signal is detected at one of the first port, the second port, the third port, or the fourth port of a driver IC, the port is configured as a clock input port based on detection of the clock signal;
- in response to the clock input port being configured, the bus controller generates and transmits a port definition code that configures the first port, the second port, the third port, and the fourth port of each driver IC according to the port mapping rule.
A bus configuration method implemented by a plurality of driver integrated circuits (ICs) coupled to a bus controller on a daisy chain connection, the method comprising:
- detecting, by one of the plurality of ports of an Nth driver IC of a plurality of ICs, a clock signal transmitted from the bus controller or from a preceding driver IC, wherein N is a positive integer;
- configuring the port of the Nth driver IC that detected the clock signal as a clock input port based on detection the clock signal;
- in response to the clock input port being configured, generating, by the bus controller, a port definition code that defines port functions of each driver IC according to a port mapping rule;
- configuring, by the Nth driver IC, its ports according to the port definition code and assigning a device identity for the Nth driver IC;
- and
- transmitting, by the Nth driver IC, a device identity command to an (N+1)th driver IC on the daisy chain to configure the (N+1)th driver IC.
Dependencies are inferred from the claim text.