Integrated chiplet-based central processing units with accelerators for video processing

A system-on-chip, comprising:

• a central processing unit (CPU)-based demultiplexer;
• a CPU-based decoding unit and an accelerator-based decoding unit coupled to the CPU based demultiplexer via a die-to-die interconnect;
• and
• an accelerator-based preprocessing unit coupled to the CPU-based decoding unit and the accelerator-based decoding unit via the die-to-die interconnect, wherein based upon an accelerator decoding configuration assessment, the system-on-chip utilizes the CPU-based decoding unit and the accelerator-based decoding unit to dynamically decode CPU-based demultiplexer output from the CPU-based demultiplexer for video processing;
• wherein the accelerator decoding configuration assessment comprises a CPU-based decoding unit software configuration assessment that includes determining whether the CPU-based demultiplexer output maps to a CPU-based decoding unit software configuration of the CPU-based decoding unit.

A system-on-chip, comprising:

• a central processing unit (CPU)-based demultiplexer;
• a CPU-based decoding unit and an accelerator-based decoding unit coupled to the CPU based demultiplexer via a die-to-die interconnect;
• and
• an accelerator-based preprocessing unit coupled to the CPU-based decoding unit and the accelerator-based decoding unit via the die-to-die interconnect, wherein based upon an accelerator decoding configuration assessment, the system-on-chip utilizes the CPU-based decoding unit and the accelerator-based decoding unit to dynamically decode CPU-based demultiplexer output from the CPU-based demultiplexer for video processing;
• wherein the system-on-chip is configured to utilize the accelerator-based preprocessing unit to dynamically preprocess decoder output from the CPU-based decoding unit and the accelerator-based decoding unit.