Near-memory operator and method with accelerator performance improvement
AssigneeSamsung Electronics Co., Ltd.
InventorsGyeongmin Lee, Bongjun Kim, Seungwon Lee, Hanwoong Jung
Life of this patent
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Abstract
A system configured to perform an operation includes: a hardware device comprising a plurality of computing modules and a plurality of memory modules arranged in a lattice form, each of the computing modules comprising a coarse-grained reconfigurable array and each of the memory modules comprising a static random-access memory and a plurality of functional units connected to the static random-access memory; and a compiler configured to divide a target operation and assign the divided target operation to the computing modules and the memory modules such that the computing modules and the memory modules of the hardware device perform the target operation.
Claims20
A system configured to perform an operation, the system comprising:
- a hardware device comprising a plurality of computing modules and a plurality of memory modules arranged in a lattice form, each of the computing modules comprising a coarse-grained reconfigurable array and each of the memory modules comprising a static random-access memory and a plurality of functional units connected to the static random-access memory;
- and
- a compiler configured to divide a target operation and assign the divided target operation to the computing modules and the memory modules such that the computing modules and the memory modules of the hardware device perform the target operation.
A processor-implemented method of performing an operation, the method comprising:
- dividing a target operation and assigning the divided target operation to a plurality of computing modules and a plurality of memory modules of a hardware device, such that the computing modules and the memory modules of the hardware device perform the target operation,
- wherein the computing modules and the memory modules are arranged in a lattice form, each of the computing modules comprises a coarse-grained reconfigurable array, and each of the memory modules comprises a static random-access memory and a plurality of functional units connected to the static random-access memory.
Dependencies are inferred from the claim text.