Ferroelectric or paraelectric based low power multiplier
AssigneeKepler Computing Inc.
InventorsAmrita Mathuriya, Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni
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Abstract
A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.
Claims17
An apparatus comprising:
- an AND gate comprising a majority gate or a minority gate having non-linear polar material;
- and
- a 1-bit full adder comprising a majority gate or a minority gate coupled to the AND gate, wherein the 1-bit full adder comprises non-linear polar material, wherein the AND gate is to receive a multiplier and a multiplicand, and wherein the AND gate comprises:
- a first capacitor to receive the multiplier, the first capacitor coupled to a node;
- a second capacitor to receive the multiplicand, the second capacitor coupled to the node;
- and
- a third capacitor coupled to a ground node, wherein the third capacitor is coupled to the node, and wherein the first capacitor, the second capacitor, and the third capacitor include non-linear polar material.
An apparatus comprising:
- a first input to receive weights including an individual weight;
- a second input to receive inputs including an individual input;
- and
- a matrix multiplier coupled to the first input and the second input, wherein the matrix multiplier includes an array of multiplier cells, and wherein an individual multiplier cell of the array of multiplier cells includes:
- an AND gate comprising a majority gate or a minority gate having non-linear polar material, wherein the AND gate is to receive the individual weight and the individual input;
- and
- a 1-bit full adder comprising a majority gate or a minority gate coupled to the AND gate, wherein the 1-bit full adder comprises non-linear polar material.
A system comprising:
- a processor circuitry to execute one or more instructions;
- a communication interface communicatively coupled to the processor circuitry;
- and
- a memory coupled to the processor circuitry, wherein the processor circuitry comprises a multiplier circuitry which includes:
- an AND gate comprising a majority gate or a minority gate having non-linear polar material;
- and
- a 1-bit full adder comprising a majority gate or a minority gate coupled to the AND gate, wherein the 1-bit full adder comprises non-linear polar material, wherein the AND gate is to receive a multiplier and a multiplicand, and wherein the AND gate comprises:
- a first capacitor to receive the multiplier, the first capacitor coupled to a node;
- a second capacitor to receive the multiplicand, the second capacitor coupled to the node;
- and
- a third capacitor coupled to a ground node, wherein the third capacitor is coupled to the node, and wherein the first capacitor, the second capacitor, and the third capacitor include non-linear polar material.
Dependencies are inferred from the claim text.