Floating-point division circuitry with subnormal support

A non-transitory computer-readable medium having instructions stored thereon that are executable by a computing device to perform operations comprising:

• performing, by floating-point circuitry, a floating-point reciprocal operation to determine a normalized mantissa value for a reciprocal of a floating-point representation of a denominator;
• performing, by fixed-point circuitry, an integer multiplication of a fixed-point representation of the normalized mantissa value for the reciprocal by a mantissa of a numerator to generate an initial value;
• and
• executing, by the fixed-point circuitry, multiple integer instructions to determine error data for the initial value and generate a final mantissa result based on the error data, including:
• using renormalization circuitry and multiply circuitry of a multi-stage pipeline of the fixed-point circuitry to execute an integer approximation instruction that generates an estimated reciprocal error based on the denominator and the reciprocal of the denominator;
• using the multiply circuitry to execute an integer adjustment instruction that generates an adjusted value corresponding to multiplication of the initial value by the estimated reciprocal error;
• and
• using the multiply circuitry and increment circuitry of the multi-stage pipeline to execute one or more integer rounding instructions that round the adjusted value based on the numerator and the denominator.

A method, comprising:

• performing, by floating-point circuitry, a floating-point reciprocal operation to determine a normalized mantissa value for a reciprocal of a floating-point representation of a denominator;
• performing, by fixed-point circuitry, an integer multiplication of a fixed-point representation of the normalized mantissa value for the reciprocal by a mantissa of a numerator to generate an initial value;
• and
• executing, by the fixed-point circuitry, multiple integer instructions to determine error data for the initial value and generate a final mantissa result based on the error data, including:
• using renormalization circuitry and multiply circuitry of a multi-stage pipeline of the fixed-point circuitry to execute an integer approximation instruction that generates an estimated reciprocal error based on the denominator and the reciprocal of the denominator;
• using the multiply circuitry to execute an integer adjustment instruction that generates an adjusted value corresponding to multiplication of the initial value by the estimated reciprocal error;
• and
• using the multiply circuitry and increment circuitry of the multi-stage pipeline to execute one or more integer rounding instructions that round the adjusted value based on the numerator and the denominator.