# US 12,523,995 B2 · Apparatus and method for manufacturing display apparatus

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- Number: US 12,523,995 B2
- Document ID: US12523995B2
- Status: Granted
- Kind: B2
- Application number: 18/343,454
- Filed: 2023-06-28
- Published: 2024-05-23
- Granted: 2026-01-13
- Earliest claimed: 2022-11-22
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Yonggu Kim
- Web page: https://patentgrep.com/patent/US12523995B2

## CPC

- G05B 19/418: Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
- G05B 19/4188: {characterised by CIM planning or realisation}
- G05B 19/41885: {characterised by modeling, simulation of the manufacturing system}
- G05B 19/4189: {characterised by the transport system}
- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G05B 2219/31001: CIM, total factory control
- G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor
- G05B: CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS (systems for controlling or regulating non-electric variables G05D; systems for regulating electric or magnetic variables G05F; control devices or systems insofar as characterised by mechanical features only G05G)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A controller includes a simulator configured to simulate a final model for converting at least one of 1-1st processors and 1-2nd processors into a down state, in a virtual space that is a virtual space, so that a filling rate, which is a ratio of a used capacity of the storage to a total capacity of the storage, is equal to or less than a first value, and a process controller configured to control a first process line according to the final model.

## Claims

### Claim 1

An apparatus for manufacturing a display apparatus, the apparatus comprising:
a first process line comprising 1-1st processors configured to process a first component into a 1-1st component, and 1-2nd processors configured to process a second component into a 2-1st component;
a second process line spaced apart from the first process line, and comprising 2-1st processors configured to process the 1-1st component, and 2-2nd processors configured to process the 2-1st component;
a storage between the first process line and the second process line, and configured to store the 1-1st component and the 2-1st component;
transporters configured to move along a transport path between the first process line and the second process line, and configured to transport the 1-1st component and the 2-1st component among the first process line, the second process line, and the storage; and
a controller configured to control the first process line, and comprising:
a simulator configured to simulate a final model for converting at least one of the 1-1st processors and the 1-2nd processors into a down state, in a virtual space, so that a filling rate, which is a ratio of a used capacity of the storage to a total capacity of the storage, is equal to or less than a first value; and
a process controller configured to control the first process line according to the final model.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the simulator comprises:
an initial model generator configured to generate an initial model for converting at least one of the 1-1st processors and the 1-2nd processors into a down state, in the virtual space, so that the filling rate is equal to or less than the first value;
a calculator configured to calculate the filling rate in the virtual space after the first process line is controlled for a first time according to the initial model in the virtual space; and
a model corrector configured to determine the filling rate in the virtual space according to the initial model is greater than the first value, and to correct the initial model into a second model.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the second model is for additionally converting one or more of the 1-1st processors and the 1-2nd processors having a highest progress rate, which is a ratio of a current processing number to a target processing number for a designated time, from a run state to a down state.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein the calculator is further configured to calculate the filling rate in the virtual space after the first process line is controlled for the first time according to the second model in the virtual space.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the model corrector is further configured to determine the filling rate in the virtual space according to the second model is greater than the first value, and to correct the second model into a third model.

### Claim 6 (depends on 4)

The apparatus of claim 4, wherein the second model is the final model, and wherein the filling rate in the virtual space according to the second model is equal to or less than the first value.

### Claim 7 (depends on 2)

The apparatus of claim 2, wherein the controller further comprises a filling rate calculator configured to calculate the filling rate after the first process line is controlled according to the final model.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the process controller is further configured to determine that the filling rate satisfies a first condition, and to convert the first process line into a down state.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the first condition indicates that the filling rate is greater than a second value that is higher than the first value.

### Claim 10 (depends on 8)

The apparatus of claim 8, wherein the first condition indicates that the filling rate is greater than the first value after the first time elapses, and wherein the process controller is configured to control the first process line according to the final model.

### Claim 11

A method of manufacturing a display apparatus, the method comprising:
locating a first process line comprising a 1-1st processor and a 1-2nd processor;
locating a second process line comprising a 2-1st processor and a 2-2nd processor, and spaced apart from the first process line;
locating a storage between the first process line and the second process line;
processing a first component into a 1-1st component with the 1-1st processor;
processing a second component into a 2-1st component with the 1-2nd processor;
transporting the 1-1st component from the 1-1st processor to the 2-1st processor with transporters;
processing the 1-1st component with the 2-1st processor;
transporting the 2-1st component from the 1-2nd processor to the 2-2nd processor with the transporters;
processing the 2-1st component with the 2-2nd processor;
transporting the 1-1st component and the 2-1st component to the storage with the transporters;
storing the 1-1st component and the 2-1st component in the storage; and
controlling the first process line by performing:
a simulation operation of simulating a final model for converting the 1-1st processor or 1-2nd processor into a down state, in a virtual space, so that a filling rate, which is a ratio of a used capacity of the storage to a total capacity of the storage, is equal to or less than a first value; and
a processor control operation comprising a final model application operation of controlling the first process line according to the final model.

### Claim 12 (depends on 11)

The method of claim 11, wherein the simulation operation comprises:
an initial model generation operation of generating an initial model for converting the 1-1st processor or the 1-2nd processor into a down state, in the virtual space, so that the filling rate is equal to or less than the first value;
a virtual space application operation comprising an operation of controlling the first process line according to the initial model in the virtual space;
a virtual space calculation operation comprising an operation of calculating the filling rate in the virtual space, after a first time elapses from a time, the virtual space application operation starting according to the initial model; and
a model correction operation comprising an operation of correcting the initial model into a second model, the filling rate in the virtual space according to the initial model calculated in the virtual space calculation operation being greater than the first value.

### Claim 13 (depends on 12)

The method of claim 12, wherein the second model is for additionally converting the 1-1st processor or the 1-2nd processor having a highest progress rate, which is a ratio of a current processing number to a target processing number for a designated time, from a run state to a down state.

### Claim 14 (depends on 12)

The method of claim 12, wherein the virtual space calculation operation further comprises an operation of calculating the filling rate in the virtual space after the first time elapses, the virtual space application operation starting according to the second model.

### Claim 15 (depends on 14)

The method of claim 14, wherein the model correction operation further comprises an operation of correcting the second model into a third model, and wherein the filling rate in the virtual space according to the second model calculated in the virtual space calculation operation is greater than the first value.

### Claim 16 (depends on 15)

The method of claim 15, wherein the second model is the final model, and wherein the filling rate according to the second model is equal to or less than the first value.

### Claim 17 (depends on 12)

The method of claim 12, wherein the processor control operation further comprises a filling rate calculation operation of calculating the filling rate after the final model application operation.

### Claim 18 (depends on 17)

The method of claim 17, wherein the processor control operation further comprises a first process line down operation of converting the first process line into a down state, wherein the filling rate calculated in the filling rate calculation operation satisfies a first condition.

### Claim 19 (depends on 18)

The method of claim 18, wherein the first condition indicates the filling rate is greater than a second value that is higher than the first value.

### Claim 20 (depends on 18)

The method of claim 18, wherein the first condition indicates the filling rate calculated in the filling rate calculation operation is greater than the first value after the first time elapses from the final model application operation.